應用於貪睡靜態記憶體之有效診斷與修復技術

Efficient Diagnosis and Repair Techniques for Drowsy Static Random Access Memories

黃秉偉(Bing-Wei Huang)

指導教授 ： 李進福

國立中央大學/資訊電機學院/電機工程學系/碩士(2008年)

摘要

在單一系統晶片(SOC)的設計中，記憶體佔有很重要的角色。而且記憶體通常佔據晶片大部份的面積。因此記憶體的良率會對整個晶片的良率有決定性的影響。如果想要提升晶片的良率，最有效的做法就是採用提升記憶體良率的技術。診斷(diagnosis)與修復(repair)是目前最常用的兩種記憶體良率提升的技術。另一方面，漏電流(leakage current)是設計深次微米單一系統晶片的另一個挑戰。貪睡記憶體(drowsy SRAM)是其中一種降低漏電流的做法。在本篇論文中，我們針對貪睡記憶體提出有效率的診斷與修復技術。 我們針對貪睡記憶體提出可以區分開貪睡瑕疵與一般瑕疵的 March D2 演算法。接著我們進一步提出可以區分開六種貪睡瑕疵的 March D6 演算法。March D6 的測試複雜度是O((10*log2N+17+9*log2W)*N)，其中N表示記憶體單元的個數；W表示記憶體單元的位元數。另外我們針對貪睡記憶體提出有效的自我修復方案。新的修復方案可以使用貪睡遮蔽暫存器(drowsy mask register)修復貪睡瑕疵。模擬結果顯示新修復方案的修復率是91%高於一般方案的修復率67%。

關鍵字

貪睡記憶體 ； 診斷 ； 自我修復

並列摘要

Memory core is one key component in system-on-chip (SOC) designs. Also, memory cores usually represent a significant portion of the chip area. Therefore, the yield of memory cores dominates the yield of the chip. Efficient yield-improvement techniques for memory cores thus are essential for improving the yield of the chip. Diagnosis and repair are two major techniques for improving the yields of memory cores. On the other hand, leakage power issue is another challenge for designing nano-scale SOCs. Drowsy static random access memory (SRAM) is one possible candidate of memory core with low-leakage power consumption. Therefore, we propose efficient diagnosis and repair techniques for drowsy SRAMs in this thesis.
First, we propose a March D2 algorithm for distinguishing drowsy faults (DFs) from non-drowsy faults (NDFs). We also propose a March D6 diagnosis algorithm for distinguishing all DFs of drowsy SRAMs. The test complexity of a March D6 algorithm is O((10*log2N+17+9*log2W)*N), where N represents the number of words of the memory under test; W represents the word width of memory. Second, an efficient built-in self-repair (BISR) scheme is proposed to repair defective drowsy SRAMs. A new redundancy analysis (RA) algorithm is proposed to allocate redundancies of the drowsy SRAM with spare rows, spare columns, and drowsy-masking registers (DMRs) [2]. The proposed BISR scheme can repair DFs by disabling the drowsy operation mode of the corresponding rows with DMRs. Simulation results show that the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the proposed RA algorithm is 91%, which is better than that of repair-most algorithm which offers 67% repair rate.

並列關鍵字

drowsy SRAM ； diagnosis ； built-in self-repair

參考文獻

[1] N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, “Circuit and microarchitectural techniques for reducing cache leakage power,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 167-184, Feb. 2004.

[2] W. Pei, W.-B. Jone, and Y. Hu, "Fault modeling and detection for drowsy SRAM caches, ” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 1084-1100, June 2007.

[3] J.-F Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, “March-based RAM diagnosis algorithms for stuck-at and coupling faults,” in Proc. Int. Test Conf. (ITC), Baltmore, Oct. 2001, pp. 758–767.

[4] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement, ” IEEE Trans. Reliability, vol. 52, no. 4, pp. 386-399, Dec. 2003.

[6] S. Hamdioui and A. J. Van De Goor, “An experimental analysis of spot defects in SRAMs: realistic fault models and tests,” in Proc. Asian Test Symposium, 2000, pp. 131-138.