多相位微波及毫米波低相位雜訊 時脈產生器之研製

Multi-phase Microwave and Millimeter-wave Low Phase Noise Clock Generators

李孟翰(Meng-han Li)

指導教授 ： 張鴻埜

國立中央大學/資訊電機學院/電機工程學系/碩士(2015年)

摘要

本論文主要是針對多相位微波及毫米波低相位雜訊訊號源積體電路的研製。首先，使用台積電0.18 μm互補式金屬氧化物半導體製程實現一個應用在2.5 GHz的多相位時脈產生器，藉由壓控延遲迴路及相位補償電路，使得輸出的相位誤差可以進一步改善。八相位時脈產生器操作頻寬為1.8 ~ 3 GHz，當輸入信號為2.5 GHz時，其輸出的最大相位誤差為2.67°，且在偏移中心頻1 kHz~40 MHz的範圍內此電路最高累計之抖動量約為627.2 fs，電路直流消耗為39.6 mW，晶片面積為0.65×0.65 mm2。
第三章提出一個應用於W頻段的高功率疊接差動壓控振盪器(VCO)，使用台積電90 nm 互補式金屬氧化物半導體製程設計和實現。為了確保疊接壓控振盪器為差動輸出
，因此可將壓控振盪器拆成等效奇模態電路和偶模態電路，在奇模態下電路必須滿足振盪條件，而偶模態電路則不會。量測輸出功率和直流轉換效率分別達到3.3 dBm和2.8%，振盪頻率可從93.6到98.7 GHz。並且使用了Q值增強架構來降低相位雜訊，相位雜訊在1 MHz頻率偏移時為-101.1 dBc/Hz，晶片面積為0.45×0.45 mm2。進一步利用此W頻段差動振盪器延生設計一個W頻段四相位振盪器，經由四個反射式的調變器將四個輸出相位整合成一個輸出，以便於W頻段四相位輸出的量測，並且對其有詳細的分析討論及模擬結果。此W頻段四相位振盪器，模擬的相位雜訊在1 MHz頻率偏移時為-93 dBc/Hz，而相位誤差與振幅誤差分別為2.37°與0.048 dB。
第四章使用延遲鎖定迴路自我對準注入的技術，實現兩個次諧波(N=16)注入鎖定鎖相迴路次諧波數(N)分別為8與16。為了進一步增加次諧波注入振盪器的鎖定頻寬，設計一個N=8的次諧波注入鎖定鎖相迴路，其模擬鎖定頻寬為59 MHz，模擬相位偵測器及迴路濾波器，最高操作頻率為312.5 MHz。N=16次諧波注入鎖定鎖相迴路量測結果在操作頻率為2.4 GHz及偏移中心頻為1 MHz時，量測相位雜訊為-124.9 dBc/Hz ，均方根值(rms)抖動為193.2 fs。最後，在第五章總結此篇論文的研究成果。

關鍵字

多相位時脈產生器 ； 微波及毫米波時脈產生器 ； 低相位雜訊時脈產生器

並列摘要

Design and analysis of multi-phase low phase noise microwave and millimeter-wave signal source intergrated circuits is presented in this thesis. A 2.5-GHz Multi-phase clock generator using a 0.18-μm CMOS process is presented in chapter 2. By utilizing a delay-locked loop (DLL) and a phase interpolator (PI), the phase accuracy of the multi-phase clock generator can be further enhanced. The bandwidth of the multi-phase clock generator is from 1.8 GHz to 3 GHz. The measured maximum phase error is 2.67°and the measured rms jitter intergrted from 1kHz to 40 MHz is 627.2 fs when the operating frequency is 2.5 GHz. The total dc power consumption is 39.6 mW. The chip size is 0.65×0.65 mm2.
A W-band high output power differential cascode voltage-controlled oscillator (VCO) using TSMC 90 nm CMOS process is presented in Chapter 3. To ensure the differential operation for the cascode VCO, the even- and odd-mode analysis is adopted in the circuit design. The proposed VCO exhibits a maximum output power of 3.3 dBm, and a maximum efficiency of 2.8 %. The measured tuning range is from 93.6 to 98.7 GHz. Also, the Q-enhancement technique is introduced to reduce the phase noise. The measured phase noise is -101.1 dBc/Hz at 1-MHz offset. The chip size is 0.45×0.45 mm2. Based on the differential cascode VCO topology, an innovative quadrature cascode VCO is proposed . The simulated phase noise is -93 dBc/Hz at 1-MHz offset and the simulated phase error and amplitude error are 2.37° and 0.048 dB.
A 2.5-GHz Subharmonically Injection-locked PLL with DLL self-aligned injection using 0.18-μm CMOS technology is presented in Chapter 4. To further increase the locking rang of sub-harmonically injection-locked VCO, two SILPLLs with sub-harmonically numbers(N) of 8 and 16 is proposed. The simulated locking range of SILVCO with N=8 is 59 MHz, and Phase Frequency Detector and loop filter are also presimulated with reference frequency of up to 312.5 GHz. As the operation frequency is 2.4 GHz, the measured phase noise of the proposed SILPLL with N=16 is -124.9 dBc/Hz at 1 MHz offset with a rms jitter of 193.2 fs. Finally, we summarize the conclusion in Chapter 5.

並列關鍵字

Multi-phase Clock Generators ； Microwave and Millimeter-wave Clock Generators ； Low Phase Noise Clock Generators

參考文獻

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