具自適應增益調整之時脈與資料回復電路

A Clock and Data Recovery Circuit with Adaptive Gain Control

陳廷宗(Ting-tsung Chen)

指導教授 ： 鄭國興

國立中央大學/資訊電機學院/電機工程學系/碩士(2015年)

摘要

隨半導體產業發展與電腦相關產業的興起，資料傳輸頻寬逐漸上升，傳統並列傳輸方式漸漸被串列傳輸取代，例如DisplayPort、SATA、USB、及PCI-E 等皆使用串列傳輸介面。本論文參考DisplayPort規格實現一個時脈與資料回復電路。 本論文實現了自適應增益調整之時脈與資料回復電路，自適應增益控制電路利用抖動量測的概念與回復時脈本身的特性，分辨輸入資料當下的相位抖動屬於高頻或是低頻。藉由調整時脈資料回復電路頻寬達到高頻與低頻的資料抖動下，皆能提高抖動容忍度。本論文使用TSMC 90 nm(TN90GUTM) 1P9M製程來實現，電路操作電壓為1 V。輸入資料速率為5.4 Gbps時，回復時脈速率為2.7 GHz，抖動量為23.11 ps(p-p)。在5.4 Gbps速率下，高頻與低頻抖動容忍度改善量分別為60.9 %與81.6 %。功率消耗為24.8 mW，晶片面積為1260 1178 um2，核心電路部分面積則為323 329 um2。

關鍵字

自適應增益控制 ； 時脈與資料回復電路 ； 抖動量測

並列摘要

In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, and PCI-E. This study presents a clock and data recovery (CDR), and takes the DisplayPort specification as reference material.
In this thesis, a CDR with adaptive gain control is proposed. The adaptive gain control circuit measures the jitter of recovered clock to detect the input data implied high-frequency or low-frequency jitter at the moment. By adjusting the bandwidth of data recovery loop, the clock and data recovery circuits can improve jitter tolerance at high-frequency and low-frequency. At 5.4 Gbps data rate, CDR jitter tolerance improvement is 60.9 percent at high-frequency, and 81.6 percent at low-frequency. This proposed was implemented by TSMC 90 nm (TN90GUTM) 1P9M process with 1 V supply voltage. When input data rate is at 5.4 Gbps, the recovered clock rate is 2.7 GHz. The period jitter of the output recovered clock is 23.11 ps (p-p). The power consumption of the CDR is 24.8 mW. The chip area is 1260 1178 um2 and the core area is 323 329 um2.

並列關鍵字

Adaptive Gain Control ； CDR ； Jitter Measurement

參考文獻

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