穩態視覺誘發電位於大腦人機介面之刺激頻率及責任週期設計

Stimulation Frequency and Duty Ratio Design in SSVEP-Based BCI System

梁家銘(Jia-Ming Liang)

指導教授 ： 徐國鎧

國立中央大學/資訊電機學院/電機工程學系/碩士(2011年)

摘要

本篇論文針對穩態視覺(Steady-State Visual Evoked Potentials, SSVEP)誘發電位之腦電訊號處理，設計一數位訊號處理硬體電路，實現具即時性的大腦人機介面系統(Brain Computer Interface, BCI)。可以有效改善目前相關研究必須建構於使用個人電腦搭配線上訊號處理軟體，以及資料擷取卡等的高成本實現方式。本研究以場可程式邏輯閘陣列(Field Programmable Gate Array, FPGA)為基礎來設計相關電路並實現穩態視覺誘發電位之硬體即時訊號處理，用以建立低成本與方便使用之BCI系統。另外，為了有效誘發SSVEP之腦電訊號，本篇論文設計發光二極體(Light-emitting diode, LED)閃爍燈號可依不同使用者之腦波反應特性，自我制定閃爍頻率以及燈號觸發責任週期，來有效誘發使用者的SSVEP，以增強訊號之訊雜比，而提高系統判斷率。最後經由實驗結果證明本系統能有效誘發出使用者之 SSVEP，達到即時SSVEP訊號辨識處理，並且能有高準確辨識率。

關鍵字

穩態視覺誘發電位 ； 大腦人機介面 ； 閃光頻率 ； 責任週期

並列摘要

This thesis proposes a low-cost field-programmable gate-array (FPGA) based steady state visual evoked potential (SSVEP) brain-computer interface (BCI) system. Most existing BCI systems use bulky and expensive electroencephalography (EEG) measurement equipment, personal computer, and commercial real-time signal-processing software. Therefore, the objective of this thesis is to establish a low cost FPGA-based BCI system with real-time SSVEP signal processing circuit. Moreover, the flashing duty and frequency of LED flicker are choose by an automatically searching procedure for each user in order to evoke SSVEP signal effectively and improves the information transfer rate (ITR). Finally, experimented results show that the SSVEP can be evoked effectively and high identification accuracy is obtained.

並列關鍵字

EEG ； flicker frequency ； duty ratio ； phase encoding ； BCI ； SSVEP

參考文獻

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