針對大規模架構探討之多核心模擬器與其可調效能分析模組

A Qemu-based Multi-core Simulator with Flexible Performance Model for Large Scale Architecture Exploration

許雅淳(Ya-Chun Hsu)

指導教授 ： 陳添福

國立中正大學/工學院/資訊工程學系/碩士(2011年)

摘要

根據近年來工業上的趨勢很明顯的表現出未來處理器可能會有出現數百甚至數千顆多核心在單一處理器上。為了加速硬體的開發，模擬器技術越顯得重要。因此模擬器無可避免的需要能夠模擬大規模架構和其龐大運算量在超多核心的現象，以提供硬體開發者參考。而這些模擬的規模和複雜度是遠遠超過現在真實機器可以執行的。此篇論文在基於Qemu的基礎上建立一個trace-driven的多核心模擬器，且將其掛上一個彈性化的效能分析模組，為此模擬器提供模擬結果的數據。在Qemu裡我們實做了一個記錄的方法，此方法可以提供足夠的資訊給效能模組做分析和產生數據。使用者也可以透過此篇論文新增在Qemu裡的裝置來控制紀錄產生器的開始時間跟結束時間。記錄產生器可以濾掉特權模式，只保留使用者模式的資訊來做效能分析。效能分析模組的設計是基於可替換模組，效能模組透過統一的介面來連接各個硬體模擬模組。所以使用者可以利用提供的模組介面撰寫他們自身需要的客製化模組，以有效讓使用者分析他們自己所需要的時間估算和效能分析需求。

關鍵字

多核心模擬器

並列摘要

It is now clear that processors with hundreds or thousands of cores will eventually be available according current industry trends. To accelerate hardware development, simulations of future multicore architecture which have huge computational resources and more complex than current machine are unavoidable. This thesis builds a trace-driven simulator based on Qemu with a flexible performance model. The trace mechanism is implemented in Qemu and supports exchanging information with the performance model. Users can control what time to start the trace and what time to finish the trace by themselves. To achieve this, this thesis adds a device on target architecture. The trace mechanism also can filter out kernel mode information and only allow user mode information to produce performance statistics. Based on swappable modules, the performance modular design offers a programming interface for integrations with other customized hardware modules. Users can use the provided module interface to write their customized modules for detailed timing models or performance-demand models.

並列關鍵字

Multi-core Simulator

參考文獻

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