低功率消耗與高效率之CMOS射頻晶片設計

Low Power and High Efficiency CMOS RFICs for Multistandard Transceivers

魏牧得(Wei, Muhdey)

指導教授 ： Negra, Renato ； 張盛富

國立中正大學/工學院/電機工程學系/博士(2012年)

摘要

本論文探討應用於新一代多頻帶多標準收發機之低功率消耗、低相位雜訊和高效率的CMOS關鍵射頻晶片。包括三個低雜訊放大器(LNA)，低功率寬頻混頻器(Mixer)，兩個低相位雜訊四相位電壓控制振盪器(QVCO)，一個低功耗電流再利用差動振盪器以及寬頻高效率之切換式射頻功率放大器(Switching-mode power amplifier, SMPA)。
第一個低雜訊放大器是採用電流再利用兩極串接架構，利用並聯共振器取代傳統的電感 ，減少使用面積。該放大器實際面積僅有 0.28平方毫米。
基於電流再利用架構 ，第二個全差動低雜訊放大器使用轉導提升技術(gm boosting)更加減少功率消耗，利用基極(body)電阻減少基版的雜訊貢獻 。此晶片整體消耗功率為1.66毫瓦 。

本論文題出一個新的可變增益(Variable Gain)技術並設計一個雙級疊接(Cascode)低雜訊放大器來驗證。加入改變增益的電晶體並聯於第一級放大器的輸出端，利用全差動訊號相位差180度的特性，改變此外加的電晶體偏壓可使增益改變。由於全差動訊號相位差180度，放大器的電流與輸入反射系數(input return loss)不會隨著增益而改變 。量測結果證實當增益由0 dB變動至12.3 dB時，直流電流僅有正負 3 %的變動，輸入反射系數也僅有正負 3 %的變動 。

接下來是一個應用雙閘極雙饋入與基極偏壓技術設計的低功耗寬頻雙平衡主動混頻器 ，有效降低功率消耗並提升轉換增益。量測電壓轉換增益為11.9 dB，僅需0.17 mW與0.6 V的供應電壓，其FOM達19.4，操作頻寬可由1.0 GHz到4.0 GHz，涵蓋目前許多規範，量測結果證實本論文提出之技術確實達到預期的目標 。

在壓控振盪器(QVCO)方面，共振腔採用新的背對背變容器串接技術 (Back-to-back series varactor) 可以有效消除振幅對相位(AM-to-PM)的雜訊，其量測的相位雜訊在 1 MHz頻率偏移時為-130 dBc/Hz ，評量指數(FOM)達到為-193.6。
本論文也還針對低功率消耗的電流再利用壓控振盪器進行研究，電流再利用VCO的主要缺點為輸出振幅不平衡，論文內提出了自動轉導補償技術，可解決輸出振幅不平衡的問題。量測結果顯示當振盪頻率在3.0 GHz時，差動輸出振幅只有 0.7 % 的誤差。

在發射端方面，本論文設計了一個寬頻高效率的E類切換式功率放大器 (Switching-mode power amplifiers , SMPA)，提出了一個新的負載轉換網絡(Load transformation network, LTN) 達到寬頻並且在晶片內整合了差動轉單端的電路(Balun)，因此大幅減少晶片尺寸。除外對E類負載轉換網絡的寬頻響應進行研究探討。此晶片最大輸出功率可達到28.7 dBm，在操作頻率2.3 GHz時，最大功率附加效率(power added efficiency, PAE)與汲極效率(drain efficiency )為 48%與 55%。

關鍵字

低電壓 ； 低功率 ； 低雜訊放大器 ； 振盪器 ； 切換式功率放大器 ； 功率放大器 ； 射頻晶片 ； 電流再利用 ； 寬頻切換式功率放大器

並列摘要

Low power, low phase noise and high efficiency radio frequency integrated circuits (RFICs) for the next-generation multiband multistandard transceivers in CMOS technology were investigated, which include three LNAs, a wideband mixer, two quadrature VCOs, a current-reuse VCO, and a switching-mode power amplifier. The first CMOS LNA is a current-reuse cascade configuration, where an interstage parallel resonating $LC$ tank is used for signal directing between the two MOSFETs. This LNA has a very compact chip size of 0.28 mm2. The $g_m$-boosting technique was applied to the above current-reuse LNA for further power consumption reduction. The body resistor was added also to decrease the substrate-induced noise.
This LNA consumes only 1.66 mW. A new variable gain (VG) technique was introduced to the current-reuse LNA, where an additional RF path is created in parallel to the first MOSFET stage.
When the RF gain is changed by the control voltage, the total bias DC current is not altered.
The experimental results show that the DC current has a $pm 3,\%$ and Ssubscript{11} has $pm 3.5,\%$ variation when the gain is tuned from 0 dB to 12.3 dB.

Next, a low power wideband double-balanced mixer was designed by using the proposed double-gate outphase feeding and backgate biasing techniques. The implemented mixer consumes only 0.17 mW from a supply voltage of 0.6 V.

On VCOs, the phase noise reduction techniques were studied for quadrature CMOS VCOs. A new LC tank with the back-to-back series varactors was examined, where the AM-to-PM noise conversion was effectively eliminated. The measured phase noise is dBcHzSI{-130} at 1 MHz offset and the FOM reaches -193.6.
Next, the common output amplitude imbalance problem of current-reuse CMOS VCOs was solved by proposing a spontaneous transconductance match technique.
The measured amplitude imbalance is less than 0.7 % in our designed 3.5 GHz CMOS VCO.

Finally, a wideband high-efficiency switching-mode power amplifiers (SMPA) in CMOS technology was investigated. New load transformation networks (LTNs) were proposed. The bondwire effect on the efficiency was examined. Furthermore, the balun was merged into the LTN such that the chip size is considerably reduced. The measured results achieve a peak output power of 28.7 dBm, power added efficiency (PAE) of 48.0 % and drain efficiency of 55.0 % at 2.3 GHz.

並列關鍵字

Current-reuse ； Low voltage ； Low power ； LNA ； VCO ； PA ； SMPA ； RFIC ； CMOS ； class-e ； power amplifier

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