高供應電源拒斥比、高速暫態反應之低壓降線性穩壓器設計

本論文提出一個適合整合於低電壓及低功率、高效能系統晶片之低壓降線性穩壓器，採用1V TSMC 90nm CMOS 製程，輸入供應電壓為1V，輸出可藉由調整迴授網路的電阻而產生介於0.85-0.5V間的電壓。由於低電壓系統對於電源品質的要求，所提出的低壓降線性穩壓器具有高供應電源雜訊拒斥比與快速暫態反應的特性，首先利用了隔離前端電源雜訊與在傳遞元件實現雜訊抵銷的設計手法可以有效改善低壓降線性穩壓器的供應電源雜訊拒斥比。此外，應用加速功率電晶體迴轉率的輔助電路則可有效提升低壓降線性穩壓器的暫態響應。模擬結果指出當負載電流由1mA變化至100mA時，PSRR在1MHz頻率內有仍可保持-50dB以上而達成良好的抑制電源雜訊效果；而0mA~100mA的暫態反應測試顯示，輸出電壓在負載改變瞬間的變異值小於±3%輸出電壓，可確保後端負載電路的供電品質而不影響其效能。此電路的電流效率為99.91%。

關鍵字

高供應電源拒斥比；低壓降線性穩壓器

並列摘要

This thesis presents an integrated Low Dropout (LDO) voltage regulator design which is suitable for low-voltage, low-power and high-performance system on a chip (SOC) application. Using the 1-V TSMC 90nm CMOS process, the proposed LDO voltage regulator can convert an input voltage of 1V to an output voltage of 0.85V-0.5V by adjusting the resistance of feedback network. With the requirement of power supply quality in low-voltage system, the proposed LDO voltage regulator have to achieve high Power Supply Rejection Ratio (PSRR) and fast transient response. First power noise isolation and ripple cancellation techniques are proposed to improve the PSRR of LDO voltage regulator effectively. Furthermore, a slew-rate enhancement circuit is applied to enhance the transient response. Simulation results show that at least -50dB PSRR is achieved at 0-1MHz for a load range of 0-100mA, while the output voltage variation is less than ± 3% of output voltage to ensure the power supply quality and performance of the load circuit. The current efficiency of the proposed LDO voltage regulator is 99.91%.

並列關鍵字

Low-Dropout (LDO) voltage regulator ； High PSRR

參考文獻

[1] K. N. Leung and P. K. T. Mok, “A Capacitor-Free CMOS Low-Dropout Regulator with Damping-Factor-Control Frequency Compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003.

[2] S. K. Lau, P. K. T Mok, K. N. Leung, “A Low-Dropout Regulator for SoC with Q-reduction,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 658-664, Mar. 2007.

[3] Gabriel A. Rincon-Mora, Phillip E. Allen, “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998.

[4] Mohammad Al-Shyoukh, Hoi Lee, Raul Perez, “A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation,” IEEE J. Solid-State Circuits, Vol. 42, no. 8, pp. 1732-1742,Aug. 2007.

[5] Peter Hazucha, Tanay Karnik, Bradley A. Bloechel ,Colleen Parsons, David Finan, and Shekhar Borkar, “ Area-Efficient Linear Regulator With Ultra-Fast Load Regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933-940, Apr. 2005.

國際替代計量

高供應電源拒斥比、高速暫態反應之低壓降線性穩壓器設計

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