近年來由於ARM處理器廣泛應用於許多嵌入式系統上,程式執行效能成為一個很重要的議題。在ARM處理器中,資料處理指令可透過指令附加S來更新狀態旗標。假設一道資料處理指令與其後面一道比較指令,兩者間存在著真相依性,若這兩道指令設定相同的狀態旗標,我們就有機會將比較指令從程式中刪除。此外我們發現若載入指令可以在ARM處理器中更新狀態旗標,則會有更多符合資格的比較指令可以予以刪除。 在本篇論文中,我們提出一套刪除比較指令的演算法,並且更改ARM模擬器Sim-Panalyzer以支援載入指令可以更新狀態旗標。我們使用一個在連結時間做最佳化且可適用於不同處理器的架構:Diablo來實作最佳化,並且使用一套可以觀察程式流程圖的工具:Lancet對程式進行分析。我們選擇了27支benchmark並且執行於ARM的模擬器 - Sim-Panalyzer。實驗結果顯示,在不用更改載入指令情況下,有一支程式可達到1.55%增速;而在更改載入指令下,有10支程式可達到1% ~ 3.81%增速。在論文最後,我們分析程式最佳化過後效能提升的根本原因並且探討了哪些特定類型的程式碼片段適用於比較指令刪除最佳化。
In the recent years, ARM architectures have been widely used on various embedded systems. Performance becomes an important issue for embedded platforms. The data processing instruction in ARM processors have the capability to update condition code flags with suffix S appended to the instruction. Suppose a data processing instruction is followed by a compare instruction, and there is a true data dependence relationship between data processing and compare instructions. It exists an opportunity to eliminate the compare instruction if both two instructions set the same condition code flags. In addition, we found that if the load instruction in ARM processors can update condition code flags, more eligible comparison instructions can be eliminated. In this thesis, we propose an algorithm to remove comparison instructions of an ARM executable. The algorithm is implemented based on the Diablo, a retargetable link-time optimization framework. The twenty-seven benchmark programs are selected and executed on an ARM simulator, Sim-Panalyzer, to evaluate the proposed algorithm. The experimental results show one program can get 1.55% speedup without the enhancement of load instruction setting condition code flags, ten programs can get 1%-3.81% speedup with the enhancement of load instruction setting condition code flags. Finally, we discuss what kind of code fragment in a program can be leveraged by our optimization of compare-instruction elimination.