- 學位論文
高能源效益之H.264視訊編解碼器晶片設計
Power Efficient H.264 Video Encoder/Decoder Chip Design
並列摘要
With the advances in the video coding algorithms, there is more and more demanded computational complexity as well as power consumption for battery-operated devices. In this dissertation, several design techniques with low operational voltage scheme are proposed to realize power efficient H.264 video coding design for battery-operated devices. The proposed design techniques which include the quality-adjustable search algorithm, the energy efficient CMOS scheme, and multiple-power domain CMOS scheme reduce the operational voltage for reducing the power consumption at the same time provide better processing performance in low operational voltage. In addition, this dissertation also provides the optimization in the aspects of algorithmic, architectural, and logic levels to reduce the memory bandwidth, hardware cost, and computational complexity to achieve the design goal of power efficient H.264 video design. Using those techniques, this dissertation proposes three power efficient designs for different battery-driven device applications. First, to achieve high throughput rates, low-power consumption, and power-aware features, we proposes a dynamic quality-adjustable H.264 baseline profile (BP) video encoder that can achieve real-time H.264 video encoding on CIF, D1, and HD720@30fps with 7mW-to-25mW, 27mW-to-162mW, and 122mW-to-183mW power dissipation in different quality modes. In addition, this chapter also proposes a dynamic quality-adjustable H.264 intra coder to encode H.264 intra video sequences on D1, HD720 and HD1080 with 10mW to 16mW, 27mW to 45mW, and 60mW power consumption under different quality modes, respectively. For low operational voltage and high processing performance features, the proposed test chip supporting low voltage (LV) H.264/AVC high profile (HP) video decoding with MBAFF coding tool is fabricated in a 90nm CMOS technology. It delivers a maximum throughput of D1@35fps at 0.5-V, which outperforms the 65nm video design at 0.5-V through a 28x improvement in throughput and provides a minimum energy consumption of 280pJ/pixel at 0.5-V as compared to the state-of-the-art H.264 video decoders. Finally, we propose a 0.4v ultra-low-energy (ULE) H.264 image/video encoder to achieve high throughput rates and low power features for wireless capsule endoscope (WCE) applications. Designed in 65nm CMOS technology at the supply voltage of 0.4v, the proposed design owns 2.5x improvement in processing throughput with 0.0196mW. Furthermore, the energy consumption of the proposed design is 14.2pJ/pixel which can achieve one order of the reduction in energy consumption as compared to state-of-the-art implementations. Moreover, in this chapter we also realize the H.264 video encoder by the same design concept with low-voltage and low-power features. Compared to previous compressors used in WCE applications, the proposed video encoder can obtain 18% reduction in energy consumption at 0.4-V.