低成本/高效率頻寬之可動態畫質調整之H.264視訊編碼器SOC架構設計

A Low-Cost Bandwidth-Efficient H.264 Video Encoder SOC Architecture Design With Dynamic Quality-Adjustability

張修誠(Chang, HsiuCheng)

指導教授 ： 郭峻因

國立中正大學/工學院/資訊工程學系/博士(2012年)

摘要

無資料

關鍵字

動態畫質調整 ； H.264視訊編碼器

並列摘要

Improving memory bandwidth efficiency of multimedia system and achieving high-definition real-time video encoding are the recent design trends in power-aware portable/vehicle/surveillance video applications, but the focus was only on low-cost, low-resolution and low-power design in the past. Furthermore, it takes a lot of hardware for high-definition video encoding associated with high external memory bandwidth and complexity to speed up to meet the requirement of real-time video encoding. As a result, developing a SOC video system that takes into account both low-cost/low-power design and high-definition real-time video encoding for power-aware video applications is a daunting challenge. This dissertation presents a low-cost bandwidth-efficient SOC architecture of H.264 video encoder with dynamic quality adjustability for power-aware video applications. We implement optimization methods in algorithm, H.264 video encoder architecture and video SOC system, respectively. First, in algorithm optimization, we propose dynamic quality-adjustable algorithms for motion estimation and intra prediction that can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. Because of the setting, computational complexity can be reduced by as high as 90%. We also propose two-stage fast MB-skip algorithm without recalculating SATD value of skip cost. The algorithm can be applied to static surveillance video applications, and it has 60% of bit-rate saving in the same PSNR value as compared to those without. Second, in H.264 video encoder architecture optimization, to simplify encoding flow and eliminate data dependence between memory data accessing and kernel core processing, we adopt six pipeline stages with the order of data pre-loading, integer motion estimation, fractional motion estimation, intra prediction, entropy coding/deblocking filtering and extended output frame buffering. In addition, we design a pre-load scheduler and an extended output frame buffer module for accessing source YUV, reference data and reconstructed data to achieve high efficiency data access with a MB-based scan order. According to the abovementioned optimization methods for H.264 video encoder architecture, we reduce external memory bandwidth by 70% by decreasing the number of R/W access from external memory, and enable H.264 video encoder to operate within a reasonable range in external memory bandwidth when targeting at high-definition video applications. In SOC video system optimization, we develop AXI-like system bus and dual direct memory access (DMA) architecture to decrease the latency of external memory accessing by using a bank-interleaving technique of DRAM, achieving 100% improvement for external memory bandwidth efficiency. With 70% of reduction of external memory bandwidth and 90% of computational complexity, the proposed H.264 video encoder SOC design can satisfy real-time performance requirement of HD (1280×720@30fps) and HD1080 (1920x1080@30fps) when operated at 90MHz and 160MHz at the cost of 485K gates and 15.2K bytes local memory according to TSMC 0.13um CMOS technology.

並列關鍵字

Dynamic Quality Adjustability ； H.264 Video Encoder

參考文獻

[3] Y. W. Huang, T. C. Chen, C. H. Tsai, C. Y. Chen, T. W. Chen , C. S. Chen , C. Fu. Shen , S. Y. Ma, T. C. Wang, B. Yu. Hsieh, H. C. Fang, L. G. Chen, "A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications," Proc. IEEE International Solid-State Circuits Conference, pp. 128-588, Febuary 2005.

[4] C. P. Lin, P. C. Tseng, Y. T. Chiu, S. S. Lin, C. C. Cheng, H. C. Fang, W. M. Chao, L. G. Chen, "A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications," Proc. IEEE International Solid-State Circuits Conference, pp. 412-413, Febuary 2006.

[7] Y. K. Lin, D. W. Li, C. C. Lin, T. Y. Kuo, S. J. Wu, W. C. Tai, W. C. Chang, and T. S. Chang , " A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip," Proc. IEEE International Solid-State Circuits Conference, pp. 314-315, Febuary 2008.

[8] Koyo Nitta, Mitsuo Ikeda, “An H.264/AVC High422 Profile and MPEG- 2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures”, International Symposium on VLSI Circuits", June, 2008.

[9] Seiji Mochizuki, Tetsuya Shibayama, et al., “A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol, 43, No. 11, Nov, 2008.