具有低功耗和低電壓操作之壓控振盪器與LTE發射機模組之設計

本論文設計0.18 μm CMOS低電壓和低功耗之壓控振盪器和LTE行動通訊射頻發射機。本CMOS壓控振盪器利用互補式PMOS 電路架構來提供負阻，根據所需頻帶設計中間抽頭的八角型螺旋電感、PMOS可變電容、與MIM電容組成共振腔來產生適當的振盪頻率範圍。PMOS可變電容是將PMOS電晶體的汲極(Drain)、源極(Source)接在一起，並給予一電壓去調控其容值，另一端單獨為閘極(Gate)，而基極(Bulk)則與汲極(Drain)和源極(Source)斷開，如此則可使電晶體不處於累增區內，基極(Bulk)要另接低於整個電路中的最高電壓，使此晶片具有低電壓和低功耗操作。其操作頻率2344 ~ 2844 MHz，有19.2 %的可調頻寬，輸出功率為-2.3 ~ -5.9 dBm,相位雜訊在1MHz量測值為-119.78 ~ -105.3 dBc/Hz，而消耗功率為2mW，晶片整體FOM為-190.8 dBc/Hz。本論文的第二部份為針對第四代行動通訊(LTE)規範整合多重微波技術實現雙頻帶教育性射頻發射機。此發射機採用雙頻超外差架構。發射機的子電路規格是先經由鏈路計算後而訂定，依子電路規格定義，設計並實現各個子電路。最後將各個子電路集合成為一個機架，該電路的順序是可以根據所需的功能而改變，而無需重新設計的支路。再進行以連續波(CW)訊號以及數位調變訊號測試以驗證設計方法。

關鍵字

發射機；壓控振盪器；低功耗

並列摘要

A low-voltage and low-power 0.18-μm CMOS voltage-controlled oscillator, using PMOS-only transistor, and LTE transmitter module ware designed in this thesis. On the CMOS VCO,the bulk of the PMOS varactor, which is disconnected with drain and source nodes, is properly biased to lower the operation voltage and power consumption. The measured operating frequency range is from 2344 to 2844 MHz, equivalently 19.2% of the tuning bandwidth. The output power is -2.3 ~ -5.9 dBm, the phase noise is -119.78 ~ -105.3 dBc/Hz , and the power consumption is 2 mW. The figure of merit is -190.8 dBc/Hz. On the LTE transmitter module, an LTE dual-band RF educational transmitter module was designed and implemented in hybrid microwave integrated technology. This transmitter uses dual-conversion heterodyne topology. The link budget was calucalted first. Then the subcircuit were defined, designed, and implemented in the board level. Finally the subcircuits were integrated in a rack such that the circuit order can be changed according to the desired function without redesigning the subcircuits. The CW signal and the digitally-modulated signal test were carried out to validate the design methodology.

並列關鍵字

LTE transmitter module ； VCO ； Low Power consumption

參考文獻

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[4] B. Razavi, “RF Transmitter Architectures and Circuits,” IEEE Custom Integrated Circuit Conference, pp. 197-204, 1999.

[5] M. Perrot et. al., “A 27-mW CMOS fractional-n sSynthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE Journal of Solid-State Circuits, vol. 32, Dec. 1997.

[6]P. Davis, “Merits and requirements of a few RF architectures”, IEEE BCTM 4.1, 1999.

[7] D. B. Lesson, “A Simplified Model of Feedback Oscillator Noise Spectrum,” Proceedings of the IEEE, vol. 42, pp. 329-330, Feb. 1965.

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具有低功耗和低電壓操作之壓控振盪器與LTE發射機模組之設計

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