應用於展頻序列通訊之全數位資料回復電路

隨著半導體科技的不斷進步，積體電路的工作時脈以及各種通訊介面的傳輸速率也越來越快。然而，越高的工作時脈與傳輸速率將使電磁干擾效應變得更加嚴重。電磁干擾效應會使電子產品在高速運作時互相影響，導致電路工作行為的不正常現象。現今已有很多種技術被提出來以解決電磁干擾的問題，各種技術中又以展頻時脈產生器最為熱門。展頻時脈產生器是在一般的時脈產生器中加入調變，使其產生的時脈訊號頻率會在一個範圍內上下擺動，達成展開頻率的效果。比起其他解決電磁干擾的技術，展頻時脈產生器的成本較低。此外，因為加入了展頻時脈，資料的傳輸速率就不再固定於某個速率上，而是在一個特定的頻率範圍。這會使得傳送端的資料被加入額外的時脈抖動影響，造成接收端的位元誤碼率上升。因此通常展頻的範圍都不會定的太大，大約都在5000ppm。然而，如果展頻的範圍可以更大(大於10%)，將會有更好的電磁干擾效應衰減效果。所以，如果接收端電路可以容忍更大的展頻範圍，這對整體電路的電磁干擾效應衰減是更有幫助的。本論文提出的全數位時脈與資料回復電路包含幾項特點以克服大範圍的展頻。內插式的震盪器微調架構克服一般串接型震盪器的周期非單調遞增行為。適應性動態增益調整以及基於時間對數位轉換器的快速相位增益補償大大地加強了一般時脈與資料回復電路在大範圍展頻 (大於10%)下追蹤能力的不足。比起一般的時脈與資料回復電路，本論文提出的電路還具有快速鎖定以及不需要參考時脈、多相位時脈產生器和超取樣式架構等優點，這也使得晶片面積、功率消耗以及硬體設計複雜度上有這顯著的下降。本論文之晶片是以90奈米製程的標準元件庫實現，具有很好的製程移轉能力。工作範圍為76MHz到480MHz，晶片面積為0.09mm2，功率消耗在480MHz且10%的向下展頻下為4.28mW。

關鍵字

時脈與資料回復電路；展頻時脈產生器；電磁干擾

並列摘要

With the great progress of the semiconductor technology, the operating frequency of ICs and the data rate of communication systems become faster and faster. However, the higher operating frequency and data rate will make more electromagnetic interference (EMI) effects. With EMI, the electronic devices will influence each other in high speed and work irregularly. There are many techniques proposed to solve the EMI problem. The spread spectrum clock generator (SSCG) is the hottest solution in all techniques. The SSCG is modulated with a spreading profile in traditional clock generators. The output frequency of the SSCG spreads out in a frequency range and achieves the spread spectrum. Comparing with other solutions for EMI, the SSCG has lower cost. In addition, with SSCG, the data rate is no longer fixed but in a certain frequency range. The transmitter will produce additional jitter to the receiver, and the bit error rate of the receiver is increased accordingly. Hence, the spreading ratio of SSCG is always chosen in a small range, such as 5000ppm. However, if the transmitter can transmit data stream with a larger spreading ratio (>10%), there will be more EMI reduction. As a result, if the receiver can tolerance a larger spreading ratio, it is very useful for EMI reduction performance of the whole circuit. In this thesis, we propose an all-digital clock and data recovery (CDR) with some features to overcome the large spreading ratio. The interpolator based fine tuning architecture of the digital controlled oscillator (DCO) overcomes the non-monotonic phenomenon of conventional cascaded DCO architecture. The adaptive control scheme and the time-to-digital converter (TDC) based fast phase compensation enhance the tracking ability of conventional CDR circuit with a large spreading ratio (>10%). In addition, the proposed ADCDR circuit performs fast lock-in and doesn’t need an reference clock, or a multi-phase clock generator and oversampling architecture. The area, power consumption and design complexity can be greatly reduced. The chip of this thesis is implemented in 90nm CMOS process with standard cells, and thus it has good portability over different processes. The core area is 0.09mm2 and the power consumption is 4.28mW at 480MHz with 10% down spread.

並列關鍵字

CDR ； SSCG ； EMI

參考文獻

[1] Serial ATA Working Group, SATA-IO Revision 3.1 Specification, July, 2011.

[2] Hsiang-Hui Chang, I-Hui Hua, and Shen-Iuan Liu, “A spread spectrum clock generator with triangular modulation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673-676, Apr. 2003.

[3] Davide De Caro, et al., “A 1.27 GHz, all-digital spread spectrum clock generator/synthesizer in 65nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1048-1060, May 2010.

[4] Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A low power and portable spread spectrum clock generator for SoC applications,” IEEE Transactions on Very Large Scale

[5] Behzad Razavi, “Challenges in the Design of High-Speed Clock and Data Recovery Circuits,” IEEE Communication Magazine, vol. 40, pp. 94-101, Aug. 2002.

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應用於展頻序列通訊之全數位資料回復電路

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