適用於寬頻通訊系統使用預測架構之連續時間三角積分調變器

Design of Continuous-Time Sigma-Delta Modulator with Forecast Architecture for Wide-Band Communication Systems

王大瑋(Da-Wei Wang)

指導教授 ： 蔡宗亨

國立中正大學/工學院/電機工程學系/碩士(2012年)

摘要

在本論文中實現了一個應用於寬頻帶通訊系統的連續時間三角積分調變器。連續時間三角積分類比數位轉換器在設計挑戰上，有時脈抖動和額外迴路延遲的問題。在本論文中主要探討額外迴路延遲的問題，一般為了解決額外迴路延遲的問題，使用雙迴路架構以容忍一個時脈週期的延遲。為了要在寬訊號頻帶的應用並且有高解析度的效能，使用高取樣頻率的話(400MHz~1GHz)，額外迴路延遲可能會超過一個時脈週期，這可能會使得調變器不穩定以及效能的降低。在本論文中探討如何延長額外迴路延遲的容忍度，並且提出的預測架構來達到增加容忍度的目標。在本論文中實現一個操作在10MHz的連續時間三角積分調變器，使用TSMC 0.18μm CMOS製成來實現，取樣頻率為400MHz，解析度為70.03dB ，功率消耗為39.08mW，晶片面積為1.721mm2。

關鍵字

連續時間三角積分調變器 ； 類比數位轉換器 ； 額外迴路延遲 ； 預測

並列摘要

This work presents the continuous-time delta sigma modulator for wide-band communication systems. The challenge of the wide-bandwidth continuous time delta sigma modulator is the clock jitter and excess loop delay. To solve excess loop delay problem, dual loop architecture is used to tolerate one clock period delay. However, with high sampling frequency (400MHz~1GHz) for wide-bandwidth applications and high resolution, excess loop delay is often more than one clock period and can make the loop filter unstable. The forecast architecture is proposed to extend the tolerance of the excess loop delay. A CT-ΔΣ modulator with 400 MHz sampling rate has been realized in a TSMC 0.18μm CMOS process, and SNDR 70.03dB in 10MHz bandwidth is achieved with 39.08mW power dissipation, the chip area is 1.721mm2.

並列關鍵字

continuous-time delta sigma modulator ； analog-to-digital converter ； excess loop delay ； forecast

參考文獻

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