經由網路晶片的學習式動態重組來支援多樣化處理需求

因為製程進步的因素，在網路晶片裡串音干擾和較高的動態功率消耗是兩個越來越需要被注意的設計考量。因為網路晶片使用了相當多的傳輸線路來進行平行溝通，因此串音干擾和動態功率消耗的問題也更為嚴重。使用資料編碼器可以降低在傳輸線路上的電位轉換次數，因而消除了一些會造成串音干擾和較高動態功率消耗的資料傳輸組合。然而，這些資料編碼器卻通常無法隨著程式的需求，系統的特性，以及使用者的喜好在動態執行過程中被客製化。再者，目前系統的一個趨勢就是在於可以支援更多且不同的程式執行。如果一個系統需要支援的程式所需的運算能力超過目前系統所能提供的，那麼這個系統在市場的存活時間通常就會被縮短。為了適應廣泛的處理需求包含可靠度，低功率，以及功能上的彈性，我們提出了一個創新且具備彈性的架構，也就是支援低功率及可靠度編碼策略的動態重組網路晶片。我們所提出的動態重組網路晶片支援各式動態硬體重組，包含處理單元，路由器，以及資料編碼器的動態重組。為了管理處理單元的動態重組，我們定義了一組相對應的程式介面來支援我們的動態重組網路晶片架構。在路由器的動態重組方面，我們提出了一個用來避免封包遺失的動態重組流程和相關的電路設計。而為了符合可靠度及低功率需求，我們提出一個創新的推論及學習的策略來達到智慧型的資料編碼器選擇。在這個推論及學習的策略裡我們是利用類神經網路根據資料編碼器的特性來加以歸類並選擇。透過權衡在可靠度和低功率的需求上，以及編碼器本身所帶來的效能及硬體資源上的負擔，來加以選擇適合的編碼器以符合動態需求。為了做概念上的驗證，我們在Xilinx 的 Virtex-4 現場可程式邏輯門陣列平台裝置上，實做了一個具備3×3 拓樸的動態重組網路晶片雛型。和一般的網路晶片相比，該動態重組網路晶片節省了8.2% 的硬體資源。而和一般使用單一固定編碼器的網路晶片相比，我們所提出的動態重組網路晶片在訊號干擾程度，程式，以及系統層級上的考量下，在平均的優勢對比於負擔的比例評估下，呈現了75.8%，44.0%，以及186.8%比例上的改進。從我們的實驗中顯示，在同樣比例的效能及硬體資源負擔下，我們所提出的動態重組網路晶片有更高的機率可以降低串音干擾和動態功率消耗。從以上的實驗中也說明了，為了能在動態時支援不同的處理需求，一個具備動態硬體重組能力的網路晶片架構是我們所需要的。

關鍵字

現場可程式邏輯門陣列平台；動態部分重組；網路晶片

並列摘要

Due to advanced process technologies, crosstalk interferences and high dynamic power consumption in a Network-on-Chip (NoC) are two increasingly problematic design issues. These problems become more severe in a NoC because of the large number of wires used for parallel communication. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic power consumption. Nevertheless, these data codecs are usually not runtime customizable to application requirements, system characteristics, and user preferences. Further, there is a growing for systems to support more and more diverse applications. If a system needs to support new applications that demand more computing power than that provided by the current system, the time in market of the system is usually reduced. To adapt to the wide range of processing requirements including reliability, power efficiency, and functional flexibility, a novel flexible architecture, called Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC), is proposed in this Dissertation. PRESSNoC supports the dynamic hardware reconfiguration of processing elements (PEs), routers, and data codecs. For managing PE reconfiguration, a set of application program interfaces (APIs) is defined for the PRESSNoC architecture. For supporting router reconfiguration, a reconfiguration flow to prevent packet loss and related circuit designs are proposed. For meeting the requirements of reliability and power efficiency, a novel REasoning And Learning (REAL) framework is proposed that can make intelligent selections of data codecs. The key strategy used in the REAL framework to classify data codecs is the Artificial Neural Network (ANN). Tradeoffs among reliability degree, power reduction, performance overhead, and hardware resource usage are dynamically investigated so as to select an appropriate data codec that meets runtime requirements. As proof of concept, a prototype of the PRESSNoC with a 3×3 mesh topology was implemented on a Xilinx Virtex-4 FPGA device. Compared to a conventional NoC, it required 8.2% lesser number of slices. Compared to a baseline NoC that uses a fixed data codec, the average benefit to overhead ratio of the PRESSNoC is greater by 75.8%, 44.0%, and 186.8%, at the bit interference, application, and system levels, respectively. Experiments show that at the same overheads of performance and hardware resources PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption. It also demonstrates the need for a dynamically reconfigurable NoC that supports hardware reconfiguration at runtime for different processing requirements.

並列關鍵字

Field-Programmable Gate Array ； Dynamic Partial Reconfiguration ； Network-on-Chip

參考文獻

[1] Hardware-Software Co-Synthesis of Hard Real-Time Systems with Reconfig-

[2] International Technology Roadmap for Semiconductors: Interconnect, Tech. report,

Semiconductor Industry Assoc. Available: www.itrs.net [Online], 2006.

[3] Advanced Hardware/Software Co-Design on Reconfigurable Network-on-Chip

Based Hyper-Platforms, Computers and Electrical Engineering 33 (2007), no. 4,

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經由網路晶片的學習式動態重組來支援多樣化處理需求

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