可工作於0.5V/1.0V並具有非對稱製程漂移容忍度之低功耗延遲線重複利用全數位責任週期校正電路

A 0.5V/1.0V Low-Power Delay-Recycled All-Digital Duty-Cycle Corrector with Unbalanced Process Variations Tolerance

李長潤(Chang-Jun Li)

指導教授 ： 鍾菁哲

國立中正大學/工學院/資訊工程學系/碩士(2013年)

摘要

由於Clock Tree Buffers本身的非對稱充、放電時間影響，當晶片上輸入各模組的時脈信號在穿越 Clock Tree 上串接的 Clock Buffers時，其責任週期將受到破壞。然而，對於高速資料傳輸電路來說，例如：雙倍資料率同步動態隨機存取記憶體 (DDR SDRAM) 與雙重取樣類比數位轉換器 (ADC) 等，它們透過參考時脈信號的正、負緣來取樣資料。參考時脈信號的責任週期誤差將導致這些電路不正常地工作。因此，我們必須在系統晶片 (SoC) 內加上責任週期校正電路 (DCC) ，將被破壞的時脈信號之責任週期校正回百分之五十。
隨著節能意識的抬頭，設計出一個低功率消耗的電子產品是必要的。根據電晶體的動態功率消耗公式，P=C(V^2)f，如果我們將供給電壓減為原本的二分之一，我們將可以節省百分之七十五的功率消耗。然而，在接近臨界電壓的工作電壓下，電晶體的充、放電速度將變得更緩慢。因此，邏輯閘本身的延遲時間也將變得更長，連帶影響整體電路的表現成果。
因此，本論文提出一個能工作在兩種電壓之下並具有非對稱製程漂移影響容忍度之低功耗延遲線重複利用全數位責任週期校正電路 (ADDCC) 並以90奈米製程標準元件庫實現。除此之外，本論文所提出之ADDCC具有以下特色：快速鎖定、低晶片面積使用率、低功耗及高校正準度的特色，適合應用在低功耗考量的裝置中。
關鍵詞：全數位責任週期校正電路、重複利用半週期延遲線、時間對數位轉換器、非對稱製程漂移容忍度。

關鍵字

時間對數位轉換器 ； 重複利用半週期延遲線 ； 全數位責任週期校正電路 ； 非對稱製程漂移容忍度

並列摘要

Due to the unbalanced rise time and fall time of the clock tree buffers, the duty-cycle of the on-chip clock may be distorted when it is distributed through the clock buffers to every module. However, for high speed data communication applications, such as double data rate synchronous dynamic random access memory (DDR SDRAM) and double sampling analog-to-digital converter (ADC), it requires to sample the input data via the positive and negative edges of the reference clock. Duty-cycle error causes malfunction in these applications. For the sake of this requirement, a duty-cycle corrector (DCC) is employed in the system-on-a-chip (SoC) to correct the distorted clock.
With the growing recognition of energy savings, designing low-power electronic devices is demanded. According to the dynamic power dissipation equation, P=C(V^2)f, if we reduce the supply voltage to one-half of the nominal voltage, it can reduce 75% of power dissipations. However, the operating voltage near to the threshold voltage makes transistors charging and discharging slower. Hence, the intrinsic delay of logic gates becomes longer and directly affects the overall chip performance.
Hence, an all-digital duty-cycle corrector (ADDCC) with dual supply voltage mode and unbalanced process variation tolerance is presented in this thesis. The proposed ADDCC is implemented in TSMC 90nm CMOS process with standard cells. The proposed ADDCC has following characteristics: fast lock-in time, low area cost, low power consumption and high precision in duty-cycle correcting. Therefore, it is very suitable for low-power applications.
Index Terms — All-Digital Duty-Cycle Corrector, Delay-Recycled Half-Cycle Delay Line, Time-to-Digital Converter, Unbalanced Process Variations Tolerance.

並列關鍵字

Time-to-Digital Converter ； Delay-Recycled Half-Cycle Delay Line ； All-Digital Duty-Cycle Corrector ； Unbalanced Process Variations Tolerance

參考文獻

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