- 學位論文
類比電路運算放大器 自動繞線
Analog Circuit Operational Amplifier Automatic Routing
摘要
自從第一個電子產品被創造後，半導體技術就以令人難以置信的速度在進步，然而類比電路佈局自動化相較於數位電路佈局自動化仍然處於起步階段，為了縮短類比電路佈局繞線的開發與設計周期，本論文加入佈局工程師的專業知識增進自動化佈局繞線的效能。 本論文提出在繞線時，採用計算雜散電容做為成本函數(Cost Function)，並對交點(Interconnection)與折角(bend)做優化。根據電路分析達成匹配條件(Matching Constraints)，以確保類比電路的效能。另外也限制了繞線必須嚴格對稱。 在自動化擺放部分則延續實驗室於2011年的實驗成果[1]，並對其進行程式最佳化、擺放的對稱性修正與製程轉移(350nm → 180nm)。 本論文在增益(Gain)上可以完全達到電路設計規格，產生出的結果能直接通過DRC、LVS驗證，有效的縮短電路設計週期，並在直角斯坦納樹(Rectilinear Steiner tree)提出改善方法，加入的元件旋轉能使[1]的面積更為縮小。 關鍵字：類比電路繞線、對稱匹配、電容匹配。
並列摘要
Semiconductor technology has made incredibly progress since the first electronic product was created. In contrast to digital circuits, however the analog circuit automatic layout tool is in its comparative infancy. In order to shorten the development and design cycle of an analog layout, we approach to the experience of engineer to increase the performance of automatic layout. Our work proposed computing parasitic capacity as cost function and optimizing segments’ interconnections and optimizing nets’ bends in routing. We mandated the symmetry nets symmetry strictly to match matching and to ensure the performance of circuit by circuit parsing. In automatic placement, we continued and optimized the work [1] of our laboratory in 2011 by modifying symmetry constraints and Process migration from 350nm to 180nm. Our work could totally achieve the circuit specification in Gain. The result of our program could pass DRC, LVS verification without manual modified and short the design cycle of an analog layout efficiently. We improved the method in Rectilinear Steiner tree and rotated the instances to compact circuit area. Keyword: analog routing, symmetry matching, capacity matching.