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  • 學位論文

具動態變異容忍能力之低電壓單端感測電路設計

Run-time Variation Tolerant Low-voltage Single-ended Sensing Design

指導教授 : 王進賢
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摘要


靜態隨機存取記憶體於嵌入式系統中佔有高度比例,主宰著系統的整體效能以及功率消耗。在可攜式行動裝置當道的現代,如何延長電池的使用週期為重要課題。直接降低嵌入式記憶體的工作電壓將有效地達成目標,而同時兼顧可靠度及速度為重要之設計考量。在近代低電壓靜態隨機存取記憶體設計中,依據可靠度與面積成本的考量互相權衡下,八顆電晶體細胞元為較佳設計策略。然而,細胞元單端架構會受到資料相依性位元線漏電流(Data-dependent bitline leakage)及PVT變異等問題的衝擊,使其難以繼續降低操作電壓,因此必須由記憶體中最重要之感測機制著手改良。本論文首先分析單端感測機制包含記憶體細胞元、位元線機制及感測放大器之設計考量。接著探討與歸納具動態變異容忍之單端感測設計方法論,包含:一、位元線漏電流預測(Bitline Leakage Prediction),不需額外的週邊電路即可動態抵抗變異問題,並節省功率消耗;二、動態轉態點感測放大器(Dynamic Trip Point Sense Amplifier),運用可自我調整操作電壓的反相器架構能偵測出漏電流與讀取電流的差別,完成正確的讀取。最後,此設計以台積電65奈米低功率製程實現於一512kb容量之靜態隨機存取記憶體中。

並列摘要


SRAM occupies so high ratio in embedded systems that dominate performance and power. In the modern times of portable devices, how to extend the battery life-time is important. Lower the voltage of memory will achieve the goals effectively, while both reliability and speed are major design concerns. In recent low voltage SRAM designs, based on reliability and area overhead simultaneously, 8T bitcell is a better strategy. However, the single-ended structure suffer from data-dependent bitline leakage and PVT variations, makes it hard to lower voltage continuously. Therefore we must improve the most important sensing scheme of memory. In this thesis, we analyze the design consideration of single-ended sensing design including bitcell, bitline scheme, and sense amplifier at first. Then we confer and generalize a methodology for run-time variation tolerant single-ended sensing design including: 1. Bitline Leakage Prediction, which without extra peripherals, not only relaxes variation problems dynamically, but also saves power consumption; 2. Dynamic Trip Point Sense Amplifier, which uses a self-adjusting-voltage inverter detecting the difference between leakage and read current for reading correctly. Eventually this work implemented in a 512kb SRAM with TSMC 65nm LP process.

並列關鍵字

variation tolerant low-voltage SRAM sense amplifier

參考文獻


[1] S. Cosemans, W. Dehaene, and F. Catthoor, “A 3.6 pJ/access 480 MHz, 128 kb on-chip SRAM with 850 MHz boost mode in 90 nm CMOS with tunable sense amplifiers,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2065–2077, Jul. 2009.
[2] A. Kawasumi, et al., “A low-supply-voltage-operation SRAM with HCI trimmed sense amplifiers,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2341–2347, Nov. 2010.
[3] Y. Niki, et al., “A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2545–2551, Nov. 2011.
[4] N. Ickes, et al., “A 28 nm 0.6 V low power DSP for mobile applications,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 35–46, Jan. 2012.
[5] N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Jan. 2008.

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