應用於超寬動態電壓調變數位系統之電路設計技術

Circuits Design Techniques for Ultra-Dynamic-Voltage-Scaling CMOS Systems

張耿瑞(Keng-Jui Chang)

指導教授 ： 王進賢

國立中正大學/工學院/電機工程學系/博士(2013年)

摘要

隨著科技的進步，從行動多媒體到醫療照護裝置，各種可攜式及智慧型電子發展亦越蓬勃，然而這些產品的使用時間往往受限於電池的容量，為了進一步延長產品的使用時間，高效節能電路已變成設計趨勢，而近年來研究發現超寬動態電壓調變系統可以讓系統達到最低之能耗，雖然其節能效果非常的優越，但當電路操作在如此寬範圍的操作電壓下亦面臨到各種設計上的新挑戰，因此本論文提出在互補式金屬氧化物半導體製程下，各種適用於超寬動態電壓調變系統之高效節能且高變異抵抗能力之電路設計技術，其範圍涵蓋邏輯閘層次、矽智材層次與系統層次。
近年來多項研究已經證明當電路操作在次臨界電壓區域可以達到最低的能耗，但是電路效能也會因此降低，為了讓超寬動態電壓調變系統能在次臨界電壓區域有更好的特性以便應用在各種行動裝置上，超寬動態電壓調變系統需要新的電路設計技巧來解決此問題。首先，我們提出了多樣強化反短通道效應之電路技術，藉此達到低操作能耗及低待機功耗。我們亦將反短通道效應與上述多樣技術適當地結合並將其實現於一64位元全加器，最後透過40奈米製程驗證並下線，當此電路操作在0.3V時，相對於傳統電路，其可以降低71%的操作能耗和68%的待機功耗。

另一方面，隨著製程的進步，晶片上的全域長導線已經變成的系統效能上的瓶頸，而當電路操作在次臨界電壓區域時，長導線問題亦變更加嚴重，為了解決這個問題，中繼器已經成為普遍的解決方法，但其亦因應用在單晶片系統中因為許多矽智財障礙物而造成其效能下降。為了解決此問題，我們提出矽智材的設計者在矽智材整合過程中嵌入中繼器之技術，換句話說，此技術利用嵌入在矽智材的中繼器將必須跨越矽智材的全域長導線加速，因此本論文將會闡述嵌入式中繼器的設計概念、實體設計以及應用實例，從實驗結果可以發現本技術不僅可以簡化單晶片系統的佈局設計，亦可以在超寬範圍的操作電壓下讓大幅降低全域導線的訊號延遲時間及功率消耗。
隨著製程的演進，超寬動態電壓調變系統效能的變異度問題亦變嚴重，傳統動態電壓調變系統必須預留安全餘裕以確保系統在電壓調變時仍可正確的運作，因此浪費掉了許多因降低電壓所省下的能耗，而剃刀式動態電壓調變系統藉由允許系統錯誤並加以修正，消除掉預留的安全餘裕問題並操作在更低的電壓下，因此得到更低的能耗，但是其往往需要額外花費數個週期以修正錯誤，這些額外花費的週期在微處理器系統可以輕易的吸收掉，但卻無法應用在固定資料吞吐量的應用中，如濾波器。因此我們發表了一個新型的動態電壓調變系統，當系統遇到資料延遲錯誤時，其可以藉由拴鎖器借取下一級管線之時間餘裕，並同時提高下一級管線的操作電壓來增加時間餘裕以吸收該資料延遲錯誤，因此本作品在系統遭受到大量資料延遲錯誤，仍可維持系統的資料吞吐量，為了驗證此電路概念，我們將此技術應用在一ANSI S1.11規格之濾波器組並透過40奈米製程驗證並下線，採用本技術之濾波器組，其最低操作電壓可以從0.5V降到0.35V，當其操作於0.36V時，其功率消耗可以降至33.3W，相較於傳統動態電壓調變技術，可以降低26.6%的功耗。
本論文發表之應用超寬電壓調變系統之多種設計技術，透過各式廣泛分析與模擬，搭配先進製程下線並驗證並測試，證明此技術可以讓超寬電壓調變系統擁有更高效節能且高變異抵抗能力。

關鍵字

製程免疫能力 ； 中繼器 ； 高校節能 ； 超寬電壓調變系統 ； 次臨界細胞元資料庫

並列摘要

Energy-efficient circuit design has become increasingly crucial for battery-operated devices in a wide range of applications from mobile multimedia to biomedical monitoring. In recent years, ultra-dynamic-voltage-scaling (UDVS) systems have become popular alternatives that achieve minimum energy dissipation. Although it is extremely energy-efficient, operating over a wide voltage range also includes many challenges. This dissertation gives comprehensive descriptions of several energy-efficient techniques for UDVS systems at the logic level, intellectual property (IP) level, and system level.
In UDVS systems, scaling the operating voltage to the subthreshold region has recently been shown to be an extremely effective technique for achieving minimum energy dissipation, but it comes at the cost of performance. For a wide range of battery-operated applications, the UDVS design requires new logic design techniques to deal with these problems over the wide voltage range, especially in subthreshold operations. We proposed several methods to deploy reverse short channel effect (RSCE) in order to reduce active energy consumption and standby power consumption. A 0.3 V 64b adder was implemented by appropriately combining RSCE with the proposed methods, and this was fabricated in a 40 nm process. Measurement results of the 0.3V 64b adders showed that the proposed RSCE-aware designs achieved a 71% improvement in active energy consumption and a 68% reduction in standby power.
On the other hand, on-chip global interconnects have become the bottleneck for high-speed circuit operations in advanced process technology, and are even more problematic when the supply voltage is scaled to the subthreshold region. Repeater insertion has become a common solution for dealing with these problems, but it has had to deal with new challenges due to intellectual property (IP) blockages in system-on-chip (SoC) integration. To solve this problem, we designed the IPs such that designers can embed repeaters in the IP for SoC integration. In other words, it allows the cross-IP interconnections to be routed over the IP by using repeaters inserted in the IP. The design concept, physical implementation, and examples of the applications of embedded repeaters are described in this dissertation. The experimental results showed that the proposed design not only makes the floor plan of the SoC easier, but that it also reduces the signal delay and power consumption of long interconnection circuits over a wide operating voltage range.
Another issue for UDVS systems in advanced CMOS process technology is their large variability in performance under PVT variations. Conventional DVS systems, which add a safety guardband to guarantee “always-correct” operations, result in a substantial portion of the energy efficiency gain from voltage scaling being lost. By allowing timing faults and voltage over-scaling, the Razor-style DVS systems recycle the energy invested in worst-case designs to improve yield. However, the recovery of timing faults incurs performance penalties, which can be absorbed in microprocessor systems, but can really complicate hardwired designs such as IIR filters. In light of this, we proposed a novel DVS technique which maintains throughput during the occurrence of many timing-faults caused by aggressive voltage scaling. In the proposed DVS system, timing-faults can be recovered immediately by the time-borrowing property of the latch in tandem with local supply voltage boosting. To demonstrate the design concepts, an ANSI S1.11 1/3-octave filter bank equipped with TBLB was fabricated in a 40nm process and then measured. The minimum achievable voltages of the TBLB filter were scaled from 0.5 V to 0.35 V whereas the minimum power was reduced to 33.3 μW at 0.36 V, representing a 26.6% reduction compared to the filter bank using traditional DVS techniques.
Several experimental chips of the proposed circuits were designed and fabricated. Through extensive analyses, simulations, fabrications, and measurements, all the proposed UDVS design techniques were verified. The circuit design techniques for the UDVS systems that were proposed in this dissertation improve energy efficiency and reliability over a wide operating range of supply voltages.

並列關鍵字

repeater ； energy-efficiency ； Ultra-dynamic-voltage-scaling ； robustness ； subthrehold cell library

參考文獻

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