使用非統一多位元保存資料暫存器於狀態保存之 電源閘控制設計

State Retention for Power-Gated Design with Non-uniform Multi-Bit Retention Registers

范國進(Guo-Gin Fan)

指導教授 ： 林柏宏

國立中正大學/工學院/電機工程學系/碩士(2015年)

摘要

使用保存狀態暫存器是目前最有效率及最有效果方法，在電源閘設計中，它可以保存進入睡眠模式裡正反器的狀態並防止流失。應用多位元的保存狀態暫存器(MBRR)較單一位元的保存狀態暫存器(SBRR)更有效能減少儲存位元大小，並且更節省漏電流，然而，過去的所有研究都是簡單採用相同位元的保存狀態暫存器(統一多位元保存狀態暫存器)，由於在數位系統中不規則的管線化深度，造成不有效的儲存位元利用率，為了提升儲存位元利用率且更進一步降低儲存位元大小，本篇論文提出第一個關於非統一多位元的保存狀態暫存器的定義及方法，實驗結果顯示我們提出的方法較過去最新的統一位元保存狀態暫存器方法能進一步降低42%的儲存位元數，並使儲存位元利用率達到100%。

關鍵字

整數線性規劃 ； 多位元狀態保持暫存器 ； 電源閘控制設計 ； 非統一

並列摘要

Applying retention registers to power-gated design has been one of the most effective and efficient approaches to keep the flip-flop states of idle circuit blocks during the sleep mode. Instead of applying single-bit retention registers, recent studies have shown that applying multi-bit retention registers (MBRRs) can effectively reduce storage size and save leakage power with slightly longer latency. However, all the previous works simply adopt MBRRs of the same bit size, or uniform MBRRs, which may fail to utilize overall storage of MBRRs due to irregular pipeline depths in modern digital systems. In order to achieve better storage utilization with even smaller storage size, this thesis presents the first problem formulation and solutions to non-uniform MBRR replacement for power gated design. Experimental results show that the proposed approach can further reduce 42% storage size in average compared with the state-of-the-art uniform MBRR replacement approach while achieving 100% storage utilization.

並列關鍵字

Integer linear programming ； Multi-bit retention register ； Power-gated design ； Non-uniform.

參考文獻

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