毫米波射頻積體電路之明確元件階層布局與固定長度微帶線繞校自動化設計

Automatic Precise Device-Level Placement and Fixed-Length Microstrip Routing for Millimeter-Wave RFICs

葉青豐(CHING-FENG YEH)

指導教授 ： 林柏宏

國立中正大學/工學院/電機工程學系/碩士(2016年)

摘要

隨者製成的進步以及物聯網的市場需求，毫米波CMOS射頻積體電路(RFICs)在這幾年發展非常迅速。由於CMOS射頻電路的效能對於布局圖的精確性、明確的元件布局以及準確的給予微帶線長度非常敏感，且是一個勞力密集與耗時的作業，也形成在產品推入市場上的主要瓶頸。本篇論文引進一個新穎且功能完整的架構，同時對毫米波射頻電路做元件布局與微帶線繞線。RFIC布局圖的結果在效能以及面積上都勝過需要調整模擬的人工布局圖，且運行時間明顯地被降低。

關鍵字

元件布局 ； 射頻積體電路 ； 物聯網 ； 固定長度微帶線繞線

並列摘要

With advancing process technologies and booming IoT markets, millimeter-wave CMOS radio frequency integrated circuits (RFICs) have been widely developed in recent years. Since the performance of CMOS RFICs is very sensitive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This work introduces a novel holistic framework for concurrent device placement and microstrip routing of millimeter-wave RFICs. The resulting RFIC layouts excel in both performance and area compared with the simulation-tuning based manual layout, while the runtime is significantly reduced.

並列關鍵字

device placement ； radio frequency integrated circuits ； IOT ； fixedlength microstrip routing

參考文獻

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