- 學位論文
多天線系統下適用256-QAM調變平行化多棵樹軟式輸出檢測器後端計算之硬體架構設計
LARGE Hardware Implementation of Bit LLR Calculation of the 256-QAM Signals in Parallel Tree Traversals for Soft-Output MIMO Detection
摘要
近年來, MIMO 技術在無線通訊中占有舉足輕重的地位。在MIMO 系統中, 檢測(detection) 是很重要的部份, 隨著hard-output detection 的發展成熟, 近幾年 衍生了許多soft-output detection 的研究, 提供soft-output 資訊給後端的decoder 。 本論文為了採用平行化多棵樹的軟性輸出搜尋檢測器, 在SDM-MIMO 多天線系統 下產生soft-output 的資訊, 利用得到的資訊計算其LLR(Log-Likelihood Ratio) 值。 在前端處理, 因為通道矩陣H 使用ORVD 分解的關係, 使得R 矩陣具有兩兩一對 的特性, 因此設計出一個可以同時運算達到平行處裡的硬體架構, 並且為了有效的 降低面積, 在256 QAM 下, 我們保留64個candidates , 分成8個clock cycle 去 處理。而此篇論文硬體架構設計前提是前端每一個clock 產生出8個candidates, 需 要8個clock 才能得到所有64個candidates, 也因為這個前提下, 每個clock 只會計 算到局部的candidates , 會影響計算的正確性, 而我們在硬體設計上也解決了此問 題, 提出了兩種硬體架構設計, 在此命名為Method 12 。而Method 1的硬體架構 中是等所有candidates 到齊之後再去做Bit LLR 的計算, 大部分為combinatorial 電路, 而且因為有使用registers 所以面積較大293.2 k(gate count) 但電路速度較快 可跑至333Mhz,Method 2為另一種電路設計大部分為sequential 電路, 取消了原本 的register 的硬體設計, 可以大幅降低電路面積, 為181.2k(gate count) 但速度下降至 167Mhz , 在架構設計完成後我們使用Xilinx 12.2進行Verilog 程式的撰寫, 並以 Matlab 程式輔助驗證程式的正確性, 最後使用Design Compiler 合成(synthesis) , 在ASIC 合成的結果Method 1最大操作頻率為333MHz , gate count 為293.2K , Method 2最大操作頻率為167 MHz,gate count 為181.2 K 。 關鍵詞-多天線, hard-output , soft-output , decoder , SDM , 樹狀搜尋, ORVD , Design Compiler , Bit LLR
關鍵字
軟式輸出並列摘要
In recent years, MIMO technology plays an essential role in wireless communications. In the MIMO system, detection is a very important part of the baseband receiver. As the development of hard-output detection techniques becomes mature, emphasis of current studies are now on developing the soft-output detection techniques to provide soft-output information to subsequent channel decoder. In this thesis, parallel multiple tree traversals for the SDM-MIMO system to generate bit LLR (Log-Likelihood Ratio) values are considered. It is known that the ORVD decomposition of the channel matrix produces R-matrix with pair-wise entries. This property is exploited in our design to produce parallel processing units in our architecture. For the 256-QAM signals and 4-by 4 antenna configuration in this thesis, a total of 64 candidates is searched by each of the 4 parallel tree traversals. Our architecture produces 8 candidates per clock cycle, indicating a total of 8 clock cycles is required to output the 64 candidates. To compute the bit LLR values, we propose two methods to find the minimum of the metrics of the 64 candidates. Method 1 waits until all the 64 candidates are output and then finds the minimum values as the bit LLR values. This method requires lots of registers to save the early generated candidates. The design of this Method 1 requires 293.K gates while operating at 333 MHz. Method 2 finds the temporary minimum values of the 8 candidates generated at every clock cycle and produces the final minimum values as the as the bit LLR values after 8 clock cycles. The advantage of this design is the less required registers. The design of this Method 2 requires 181.2.K gates while operating at 1673 MHz.