- 學位論文
多天線系統下適用於256QAM調變平行化多棵樹之軟性輸出搜尋檢測器硬體架構設計與實現
Hardware Architecture Design and Implementation of Parallel Multi-Tree Traversals for Soft-Output MIMO Detection of 256-QAM Signals
摘要
本論文主要探討在適用於256QAM 調變4x4 SDM (spatial division multiplexing) MIMO 系統下，使用 Soft-Output解碼，並選用LORD (Layered Orthogonal lattice detector)演算法作為樹狀搜尋的前置處理。 在本論文中採用ORVD (orthogonal real-valued decomposition) 演算法將複數訊號模型轉為實數訊號模型，且選擇LUT (look up table) modify FSD為樹狀搜尋的演算法。因為通道矩陣H 使用ORVD 將複數訊號模型轉成實數訊號模型，使得R 矩陣具有成對的特性，可設計出一個運算同時平行處理的硬體架構。為了能夠降低計算複雜度、減少面積，此篇論文採用在樹狀搜尋的最上層用LUT去選點，接下來的每一層都只保留一個最接近的子節點向下搜尋。在256 QAM下，總共保留64個 candidates，分成8個 clock cycle 去處理。在硬體架構設計完成後，使用Xilinx 12.2 進行 Verilog 程式的撰寫，並使用Matlab 程式輔助驗證，最後使用CIC提供的 Design Compiler去做合成 (synthesis), 在ASIC合成的結果最大操作頻率為120MHz, gate count 為1615K, 吞吐量為480Mbps
並列摘要
In this thesis,we consider parallel tree traversals to provide soft-output detection for the 256-QAM signals transmitted over 4x4 SDM MIMO system. The orthogonal value decomposition (ORVD) technique is used to convert the complex-valued MIMO model to the real-valued one. The R-matrix in this model has the pair-wise entries. To improve the implementation efficiency, we use look-up table to expand child nodes at the top layer of each tree traversal, and expand only one child node, i.e., the closest-point child node, in the remaining layers. A total of 64 candidates are expanded for each tree. Our architecture requires 8 clock cycles to finish the tree traversal of 64 candidates. The hardware designed architecture was implemented by Verilog code, function-verified by Xilinx ISE, and synthesized by Design Compiler. The designed architecture requires 1615K gates and provides detection throughput rate 480Mbps with working frequency 120MHz under the TSMC 90 nm CMOS technology.