晶片系統應用之抗製程與電壓變異全數位溫度感測器設計

All Digital Temperature Sensors with Anti Process and Voltage Variation for SoC Applications Design

李仁翔(JEN-HSIANG LEE)

指導教授 ： 王進賢

國立中正大學/工學院/電機工程學系/碩士(2016年)

摘要

本論文提出一個晶片系統應用之抗製程與電壓變異全數位溫度感測器設計，首先統整了相關抗製程變異溫度感測器設計，從感測原理、感測元件、感測架構、校正和最重要的三種標準化，除法、旋轉、適應型，接著以同溫度感測器架構不同製程測試，從90奈米、40奈米到28奈米，再配合3種標準化驗證各製程及標準化對抗製程變異及抗電壓變異成效，最後此作品提出室溫再校正技術，結合晶片系統及產業量產概念設計，此技術能夠有效減少電壓變異對溫度感測器影響，並在90奈米除法標準化下能將誤差-9.7~9.9˚C降低到-2.2~2.6˚C，40奈米旋轉標準化下能將誤差-10.6~11.9˚C降至-1.1~4.2˚C，28奈米適應型標準化能將誤差>±100降至-4.7~4.9˚C。

關鍵字

抗電壓變異 ； 數位溫度感測器 ； 抗製程變異

並列摘要

This paper presents a digital temperature sensor design with Anti process and voltage variation for SoC applications. First, introduce and integrate Anti process variation design from sensing principle, sensing component, temperature sensor architecture, calibration, and three normalizations about Division, Rotation and Adaptive. Second, three normalization are effective in resisting process variation, but it can’t resist voltage variation. Last, this paper presents Recalibrating technique. It combines SoC application with mass production. Recalibrating technique is effective in resisting voltage variation. Use Recalibrating technique, error from -9.7~9.9˚C reduce to -2.2~2.6˚C in 90nm Division normalization; error from -10.6~11.9˚C reduce to-1.1~4.2˚C in 40nm Rotation normalization; error from more than ±100˚C reduce to-4.7~4.9˚C in 280nm Adaptive normalization.

並列關鍵字

Anti Voltage Variation ； Digital Temperature Sensor ； Anti Process Variation

參考文獻

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