應用於多功能晶片系統之高效率直流轉直流電源轉換器設計

HighEfficiency DC-DC Converter Designs for Multifunction SoC

陳照群(CHAO-CHUN CHEN)

指導教授 ： 黃崇勛

國立中正大學/工學院/電機工程學系/博士(2016年)

摘要

可攜帶式電子產品的盛行(如智能手錶與智能手機)造就了整合多種高效能、低功耗以及多功能系統單晶片的蓬勃發展; 為了延長電池使用時間，多功能系統單晶片需要整合電源管理晶片來依據工作狀態動態調整系統內不同區域的操作電壓，因此為了因應不同電路區塊的電壓需求，電源管理晶片需要整合多種電源轉換器來達成目的。例如在寬負載範圍下具有高轉換效率的切換式電源轉換器常被做為主要的預先電壓調節器，而後承接數組具有快速暫態響應的後端電壓調節器來做為乾淨的電壓輸出。由於多功能單晶片系統往往操作於長待機或是低功率模式，同時不同工作模式的切換也會造成電流需求的急遽變化，因此具有高轉換效率、低輸出電壓鏈波和對於電流變異有快速動態響應的電源管理晶片在多功能系統單晶片設計中是不可或缺的。
為了達到以上所述目的，在此論文我們首先發表一具有功率損耗感知以及能量需求切換調變的控制行為來達到高效率、以及高效能的直流轉直流電源轉換器設計。首先，我們提出可適用於寬負載範圍下分析的功率損耗模型，針對諸多功率損耗進行公式修正，令設計者可以藉由此精準的模型預測電源轉換器各個參數的設計範圍。而藉由此模型分析，具備功率損耗感知以及能量需求切換調變機制可以在不同負載範圍針對其關鍵功率損耗有下列四項切換行為:切換功率電晶體開關狀態/切換功率電晶體尺寸/切換開關截止時間/切換控制電路的使用時間。因此搭配此技術的直流轉直流電源轉換器不需要額外的模式偵測與切換電路即可以即時依照後端應用的能量需求以及自身的功率損耗狀況彈性且迅速的調整控制行為，藉此同時達到高轉換效率、快速動態響應以及穩定的電壓調節等效能。搭配此技術的降壓型切換式電源轉換器是使用台積電90奈米製程完成晶片製作，在3.3伏特輸入/1.8伏特輸出的條件下於1毫安培-500毫安培此極寬電流負載範圍下可達到高於90%的轉換效率，並且於0.1毫安培-500毫安培的動態負載電流抽載條件下可以達到小於50毫伏特的電壓變異以及少於25 微秒的電壓回復時間。
接著我們使用此具備功率損耗感知以及能量需求切換調變機制的降壓型切換式電源轉換器作為主要調節器並連接數組線性穩壓器來達到對於電流負載變異具有快速響應的電源管理晶片設計。主要概念是使用線性穩壓器的快速響應(快速迴路)特點來實現一輔助調節迴路，藉由線性穩壓器的即時反應、即時回饋負載變異資訊至主要調節器迴路，電源管理晶片在面臨劇烈的電流負載變化下的動態效能即可以獲得有效的改善，而同時各輸出電壓之間的相互穩壓干擾現象也可以有效地消除。此具有輔助調節迴路之多輸出快速暫態響應電源管理晶片設計同樣是經由台積電90奈米製程完成晶片製作與驗證。
本論文發表之電源轉換器之設計技術，經由仔細的分析、模擬、實做以及驗證，可以證明極適合應用於現今多功能晶片系統之應用中，並同時具有極佳的未來發展性。

關鍵字

直流轉直流電源轉換器 ； 電源轉換器 ； 電源管理晶片 ； 多功能晶片系統 ； 高轉換效率 ； 功率損耗模型

並列摘要

Wearable and portable devices (e.g., smart watches and smart phones) have become mainstream technology but place ever-increasing demands on high-performance, low-power, multi-function SoCs and multi-processors. To extend battery life, the integrated power management IC (PMIC) may adaptively adjust the operating voltage for each voltage domain depending on the workload. Such a PMIC often requires several integrated regulators, where a main switching converter offers a high conversion efficiency over a wide load current range while several post-regulators provides clean outputs with fast transient response. Since the load current profile of the power managed multi-function SoC shows a fluctuating behavior with a long standby/power down period, a high performance PMIC which achieves high conversion efficiency, accurate outputs with low output ripples, and fast transient response, is indispensable.
This dissertation first proposes a novel power-loss-aware switch-on-demand modulation (PLASOM) technique based on accurate power loss modeling to switch critical components/parameters of power loss on demand: the on/off status and the size of the power transistor, the dead time, and the on/off status of power-hungry sub-circuits. A PLASOM based switched-inductor buck converter can then work as either an adaptive on-time mechanism with constant frequency or a cycle-extended adaptive on/off-time mechanism with variable frequency without mode detection/change, so that the conversion efficiency and transient response can be improved accordingly. A test chip of the PLASOM based switched-inductor buck converter was implemented using the TSMC 90 nm 1/3.3–V CMOS process. Experimental results show that a conversion efficiency higher than 90% was achieved over the 1 – 500 mA load current range, whereas the voltage variation/recovery time during the 0.1 mA – 500 mA load transient were less than 50 mV/25 s. Performance evaluations indicate that the proposed PLASOM technique is favorable for wide load current range buck converters in terms of conversion efficiency, transient response, and voltage ripples.
Furthermore, a fast PMIC with adopting the PLASOM based switched-inductor buck converter as main global power supply and several LDO regulators as local power supplies was proposed. The concept of auxiliary regulation loop is raised to take the advantage of fast LDO regulators. A test chip of the fast PMIC with the proposed auxiliary regulation loop was also implemented using the TSMC 90 nm 1/3.3–V CMOS process, and experiment results show that the transient response of the main switched-inductor buck converter was greatly improved while the cross-regulation phenomenon of the overall PMIC is greatly eliminated.
In summary, a complete design procedure of a high-performance PMIC was demonstrated in this dissertation, where modeling, architecture, circuit designs, physical implementations, simulations and chip measurements are thoroughly considered. The experimental results also verify the feasibility of the proposed techniques.

並列關鍵字

DC-DC converter ； power converter ； power management IC ； Multifunction SoC ； high power efficiency ； power loss model

參考文獻

[Online]. Available: https://www.cool3c.com/article/100824.

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