非同步硬體物件電路的設計與實作

Design and Implementation of Hardware Objects Based on Asynchronous System Technology

吳鴻基(Hung-Chi Wu)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2005年)

摘要

本篇論文提出一個具有開創性的新方法，能夠在非同步電路中實作出具有重覆使用的硬體物件。我們提出四種設計硬體物件的方法，藉由EDA Tools ALTERA實作模擬結果，分析它們實作的硬體成本與執行效能，進而找出具有簡單、快速方式來設計非同步物件功能的系統單晶片(System-on-a-chip，SoC)，而使SoC具有重複使用、適宜的效能、低能源消耗和較少的硬體成本。我們利用Object-Reference 方法，透過SOCAD tool的轉換，自動化利用非同步元件庫成功實作出具有軟體物件重覆使用的RSA加解密Engine與Stack 電路。未來將此些方法整合於我們的SOCAD開發工具內，使SOCAD tool 更能轉換出具有軟體物件導向特性的SoC。

關鍵字

硬體物件 ； 非同步電路設計 ； IP 重複使用 ； 單晶片設計

並列摘要

This thesis proposes a novel approach to implement reusable hardware objects based on asynchronous system technology. Four hardware object design schemes are proposed and the performance evaluation toward these schemes is carried out by using ALTERA Quarus II. Stack and RSA decryption/encryption IPs are implemented to demonstrate the concepts.
Our goal is to implement reusable hardware objects with adequate performance, less EMI and low power consumption based on asynchronous system technology.

並列關鍵字

Asynchronous circuits design ； Hardware Objects ； IP reuse ； soc design

參考文獻

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