管道式快速傅立葉轉換器之FPGA有效率 實現設計

AREA-EFFICIENT FPGA IMPLEMENTATION OF RADIX-4 PIPELINED FAST FOURIER TRANSFORM PROCESSOR

江建銘(Chen-Ming Chung)

指導教授 ： 汪順祥

大同大學/電機資訊學院/通訊工程研究所/碩士(2004年)

摘要

本論文先介紹幾種基本DIT和DIF的傅立葉演算法並分析比較其算術複雜度，接著敘述兩種FFT 的結構，包括管道式和以記憶體為基本的FFT結構。因為我們在實現上大部分硬體面積都花費在乘法器上，所以我們除了把每一級的乘法器縮減為一個之外，並且利用CORDIC Operator去簡化所有的”twiddle factor”運算，最後我們提出一個簡化傅立葉轉換器面積的架構，並且在FPGA上面實現它。

關鍵字

快速傅立葉轉換 ； 管道式

並列摘要

This paper introduces several algorithms and compares the computational complexity first. Second, we introduce two FFT (Fast Fourier Transform) architectures and it includes of pipelined based architecture and memory based architecture. Because we cost a lot of area size in multiplication, we reduce the multiplication in each stage. And then we use the CORDIC (Coordinate Rotation Digital Computer) operator to reduce the computation of twiddle factor. Finally, we propose a new architecture to minimize the area size and implement it in FPGA.

並列關鍵字

fast fourier transform(fft) ； pipeline

參考文獻

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