瞬間指令完成計數:一個同步多線程的提取引擎

同步多線程(SMT)是一種允許在每一個週期能夠同時發派來自不同獨立的應用程式或是線程的指令的一種技術。提取單元一直被認為是同步多線程的主要瓶頸所在，過去許多研究曾提出過一些提取策略來增進提取效率以及整體的效能。在此篇論文，我們提出一個全新的提取策略，稱之為瞬間指令完成計數(ICC)，它會計算每個線程在每一個時脈確認完成的指令數目，然後依照這些資訊來決定下一個週期要從哪些線程來提取指令。此外，我們還將此提取策略和被稱之為提取偏向(FB)和提取閘控優選(FGAP)的分支機制做結合，來建構更有效率的提取單元。經由模擬結果顯示，整體效能提升大約百分之十三，並且還減少了發派佇列的使用大小，同時還減少錯誤路徑指令的提取。另外，我們還展示負載平衡的狀態，這是過去相關研究沒有詳細討論過的議題。

關鍵字

提取策略；同步多線程；提取單元

並列摘要

Simultaneous Multithreading (SMT) is a technique that permits multiple instructions from multiple independent applications or threads to issue each cycle. While the fetch unit has been identified as one of the major bottlenecks of SMT architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency and overall performance. In this paper, we propose a novel fetch policy called Instantaneous Commit Count (ICC) which counts each thread’s retired instructions each cycle then properly selects which threads to feed next cycle. We also combine this scheme with branch mechanisms, named FB and FGAP, to construct the effective fetch unit. Simulation results show that the overall performance is improved about 13% on speedup, the issue queue size is reduced and the wrong-path instructions fetch are also reduced. Furthermore, we show the state of load balance that never discussed in prior works in detail.

並列關鍵字

Fetch Policy ； Fetch Unit ； Simultaneous Multithreading

參考文獻

[1] D. Tullsen, S. Eggers, and H. Levy, “Simultaneous multithreading: Maximizing on-chip parallelism,” In 22nd Annul International Symposium on Computer Architecture, June 1995, Pages 392-403

[3] S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, and D. Tullsen, “Simultaneous multithreading: A platform for next-generation processors,” IEEE Micro, Sep. 1997, Pages 12-18

[4] D. Madon, E. Sanchez, and S. Monnier, “A Study of a Simultaneous Multithreaded Architecture,” In Proceedings of EuroPar'99, Toulouse, Lectures Notes in Computer Science, Volume 1685, Springer-Verlag, Sep. 1999, Pages 716-726

[5] D. Tullsen and J. Brown, “Handling Long-latency Loads in a Simultaneous Multithreading Processor” MICRO-34, Dec. 2001, Pages 318-327

[6] D. Marr, F. Binns, D. Hill, G. Hinton, D. Koufaty, J. Miller and M. Upton, “Hyper-Threading Technology Architecture and Microarchitecture” Intel Technology Journal Q1, 2002

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瞬間指令完成計數:一個同步多線程的提取引擎

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