使用FPGA設計與實現AES-OCB模式運算

An FPGA design and implementation of the AES in OCB mode of operation

張毓唐(Yu-Tang Chang)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2005年)

摘要

本論文中，我們使用FPGA(X2CV-1000, 0.18μm CMOS process, 3.3V power supply)設計AES-OCB模式運算，我們利用Verilog、Xilinx ISE 6.1、ModelSim 來設計、模擬與實現。其CLB slices為3552，最大的工作頻率為61.31Mhz，資料處理量為603Mbps。

關鍵字

模式運算

並列摘要

In this thesis, we use FPGA(X2CV-1000, 0.18μm CMOS process, 3.3V power supply) to design AES_OCB mode operation. We use Verilog, Xilinx ISE 6.1 and ModelSim to design simulate and implement. The number of CLB slices is 3552.The operating clock rate is 61.31MHz. Data throughput is about 603Mbit/sec.

並列關鍵字

AES OCB FPGA

參考文獻

[3] Chitu, Cristian and Manfred Glesner et al., “An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation,” Microelectronics Journal Volume: 36, February 2005, pp 139-146.

[4] F. X. Standaert et al., “A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES Rijndael,” The Field Programmable Logic Array Conference, Monterey, California , February 23-25, 2003, pp.216-224.

[6] X. Zhang, and K.K. Parhi, “Implementation Approaches for the Advanced Encryption Standard Algorithm,” IEEE Circuits and Systems Magazine 2 (4) (2002) pp. 25–46.

REFERENCE

[1] J. Daemen and V. Rijmen, AES submission document on Rijndael, Version 2, September 1999. (http://csrc.nist.gov/CryptoToolkit/aes/rijndael/Rijndael.pdf)