P-WP 快取記憶體

P-WP Cache

許肇展(Jau-Jan Shiu)

指導教授 ： 謝忠健

大同大學/電機資訊學院/資訊工程學系所/碩士(2004年)

摘要

這篇論文關注於集合關連式快取記憶體在架構上維持高效能的情況下減少其能量消耗。我們藉由利用之前提出的階層快取記憶體、位預測快取記憶體、和看守標籤來提出P-WP快取記憶體去減少傳統關聯式快取記憶體的能量消耗。P-WP快取記憶體採用階層快取記憶體的政策、位預測快取記憶體的位預測機制、和看守表。結果顯示P-WP快取記憶體比傳統關聯式快取記憶體平均減少其能量消耗達58%、72%、84%、90%，這是個別地針對關聯為4位、8位、16位、16位來說。

關鍵字

看守標籤 ； 位預測快取記憶體 ； 階層快取記憶體 ； 集合關連式快取記憶體

並列摘要

This paper concentrates on reducing energy consumption while maintaining high performance in architectural level for set-associative cache. We propose P-WP cache to reduce energy consumption of conventional set-associative cache by exploiting advantages of previously-proposed phased cache [1], way-prediction cache [1][2], and sentry tag [12]. We apply probing policy of phased cache, way prediction mechanism of way-prediction cache, and sentry table. Results show that P-WP cache averagely reduces energy consumption than conventional set-associative cache 58%, 72%, 84%, 90% for associativity 4, 8, 16, 32, respectively.

並列關鍵字

phased cache ； sentry tag ； set-associative cache ； way-prediction cache

參考文獻

[1] Inoue, K., Ishihara, T., Murakami, K., “Way-predicting set-associative cache for high performance and low energy consumption,” International Symposium on Low Power Electronics and Design, 1999.

[2] Murakami, K., “Current status of PPRAM,” 6th International Conference on VLSI and CAD, 1999.

[5] Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi, “Improving Cache Power Efficiency with an Asymmetric Set-Associative Cache,” Workshop on Memory Performance Issues, 2001.

[6] Brannon Batson, T.N. Vijaykumar, “Reactive-associative caches,” International Conference on Parallel Architectures and Compilation Techniques, 2001.

[7] Zhichun Zhu, Xiaodong Zhang, “Access-mode predictions for low-power cache design,” IEEE Micro, vol. 22, 2002.