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  • 學位論文

同步多線程架構提取與發派引擎改善之研究

A Study of Improving Fetch and Execute Engine for Simultaneous Multithreading Processors

指導教授 : 謝忠健
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摘要


同步多線程是一種結合了傳統超純量微處理器與多線程微處理器兩者硬體特性的單一微處理器設計技術。使用同步多線程之目的在於藉由動態分享線程之間的微處理器資源來利用指令平行度與線程平行度。為了增加系統的資源利用度與產能,同步多線程的微處理器有能力在單一的週期從多個獨立的線程中提取指令來發派。在同步多線程微處理器中,提取單元已經被證實是一個同步多線程架構主要的瓶頸。許多的提取策略已經被提出用來改善發派的效率與整體的效能。然而,僅僅只有少量的研究將焦點放在同步多線程微處理器的發派緩衝區與方案上。 在這篇論文中,對於分散式的同步多線程微處理器的指令佇列我們提出一個新的提取策略與發派方案。我們依據線程的數目加入了稱為RIC的計數器當成我們的發派計劃來增加硬體資源的利用度與線程的平行度。模擬的結果顯示與基礎線相比較我們的方法最多可以達到18.9%的改善。接著,為了得到更多的效能,我們將我們的發派方案與ICC提取策略做結合。此外,由於結構危障,我們設計了一個排程器來管理並仲裁共享硬體資源的使用。最後,我們討論SMT架構的負載平衡。這個議題在之前的研究中並未被詳細討論。

並列摘要


Simultaneous Multithreading (SMT) is a single processor design technique that attempts to combine both the hardware features of conventional superscalar and multithreading processors. The purpose is to exploit the Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) by sharing the processor resources between threads dynamically. In order to increase system resources utilization and throughput, SMT processors have the ability to fetch multiple instructions from multiple independent threads to issue at a single cycle. The fetch unit has been identified as one of the major bottlenecks of SMT architecture. Lots of fetch policies were proposed to enhance the fetching efficiency and overall performance. However, only a few studies focused on the SMT processor issue buffer and schemes. In this thesis, we propose a novel fetch and issue scheme based on distributed instruction queuing buffer in SMT architecture. We add per-thread counters called RIC as our issue scheme to increase the utilization of hardware resources and thread-level parallelism. Simulation results show that our method can improve the performance by 18.9% over baseline. Then, we combine our issue scheme with instantaneous commit count (ICC) to gain more performance. Furthermore, due to structure hazard, we design a RIC scheduler to mange and arbitrate the use of shared hardware resources. Finally, we discuss the load balance on SMT architecture. This topic is never discussed in prior works in detail before.

參考文獻


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