單晶片網路之可擴充性仲裁器的設計與實作

Design and Implementation of Scalable Arbiters for SoC On-Chip Network

呂巧薇(Chiao-Wei Lue)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2008年)

摘要

SoC現在是電子業者一個熱門的話題，使用SoC有很多好處，像是成本降低、體積縮小、耗電量降低等等，但同樣也有設計上的挑戰，例如系統複雜度就是其中一個，因此市場上使用系統匯流排架構與現有的IP Cores作為整合。
在匯流排系統當中，仲裁器的角色是很重要的，因此本篇論文設計具有可擴充性的仲裁器，其仲裁演算法能夠讓使用者自行定義，此仲裁器架構可以解決傳統仲裁器不能擴充的缺點，隨著SoC高度整合的趨勢發展，當系統越來越大，具有一個可擴充性的仲裁器是不可或缺的。
我們除了提出兩個架構，還針對以優先權為基礎演算法的仲裁器架構，在硬體成本以及整體Clock所需的時間上面各提出方法做改善，並且與Round-Robin(RR)演算法比較，我們使用VHDL語言來撰寫，在Quartus上面做驗證，最後實驗結果顯示，在第四種架構的設計中，當Master IP的個數大於64時，所需的硬體成本只有RR演算法的0.89倍，而四種架構中，在Master IP個數大於16個時，整體Clock所需的時間皆比RR演算法所花的時間短，最短所花的時間只為RR演算法的0.43倍。

關鍵字

可擴充性 ； 系統匯流排 ； 仲裁器

並列摘要

System-on-chip (SoC) design is very popular in electronic industry. There are many advantages by using SoC design, such as cost down, area reduction, and low power consumption. But it also brings a lot of challenges like system complexity. Hence, many systems are integrated with existing IP cores by using on-chip communication architecture.
An arbiter plays an important role in the on-chip communication architecture. The purpose of this thesis is to design scalable arbiters and the users can define their arbitration algorithms. With high integrations, having a scalable arbiter is indispensably.
Besides, we also proposed two more designs to improve the hardware costs and the speed for the priority based arbiter architecture. The designs are written in VHDL language and verified in Quartus. The experiment results which were compared to Round-Robin (RR) algorithm show that the logic element of the architecture IV is 0.89 times the RR algorithm. All the total clock time of the four architectures are shorter than the RR algorithm and the shortest one is 0.43 times the RR algorithm.

並列關鍵字

Scalable ； Bus communication architecture ； Arbiter

參考文獻

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