採用無負載及運算放大器重設切換技術之一伏特十位元5-MS/s 管線式類比數位轉換器

A 1-V 10-BIT 5-MS/S PIPELINED ADC USING LOADING-FREE AND OPAMP-RESET SWITCHING TECHNIQUES

余尚珉(Sheng-Min Yu)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2008年)

摘要

電晶體臨界電壓雖然會隨製程精進而下降，但因漏電流等因素其 下降率不大，所以以往在管流式類比數位轉換器的電路在低電壓的情 況下不能獲得足夠的動態範圍。因此，有些方法被提出以克服這個問 題。在本篇論文中，我們使用差動式運算放大器重設切換技巧設計出 一個10 位元5Msample/s 低電壓的管流式類比數位轉換器。同時應用 一種新的低負載架構去降低電容性負載進而改善工作速度。一些常見 應用在低電壓的方法，也同時在本篇論文中加以描述。

關鍵字

類比數位轉換器 ； 低電壓

並列摘要

Because the threshold voltage of transistors does not scale with the
technology, circuits used in the pipelined ADC in the past could not
obtain the desired dynamic range in low voltage. Several solutions have
been proposed to overcome the problem. In this thesis, a 1-V 10-bits
5Msamples/s pipelined ADC is designed using the fully differential
opamp-reset-switching technique (ORST) to circumvent the speed
problem of switched-opamp technique. A novel loading-free architecture
is also employed to reduce the capacitive loading and to improve the
speed in low-voltage technique. In addition, several approaches to
overcome the low voltage issue are also described.

並列關鍵字

analog-to-digital converter ； low voltage

參考文獻

[1] M. Waltari and K. Halonen, “1-V, 9-Bit, Pipelined Switched-Opamp ADC,” IEEE

Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599–606,

May 1999.

Switched-Opamp Pipelined ADC Using Loading-Free Architecture,” IEEE J.

[5] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and