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  • 學位論文

動態收集非分支指令以減少動態分支機制之查詢

Reducing Dynamic Branch Predictor Table Lookups by Dynamically Collecting Non-branch Instructions

指導教授 : 謝忠健
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摘要


在本篇論文中,提出新的機制使用動態收集非分支指令減少對於動態分支預測的查詢,藉此達到減少在傳統動態分支預測機制下每個週期查詢所消耗的能源。在所提出的機制下,分支目標緩衝器被修改用來記錄非分支指令的個數,因此在指令擷取階段從分支目標緩衝區除了讀出目標位址之外也可得知接下來需要執行幾個非分支指令並且不去查詢動態分支預測以達到減少不必要的查詢所消耗的能源。Wattch與SPECcpu2000提供的整數與浮點數標準檢查程式被使用來評估所提出機制的能源消耗與效能並且使用SimpleScalar模擬提出的架構。實驗的結果顯示與基本架構比較使用所提出機制的動態分支預測能源消耗分別於SPECint2000減少了63.79%與SPECfp2000減少了76.58%,並且伴隨著可忽視的效能減少。

並列摘要


This thesis proposes a new scheme of dynamically collecting non-branch instructions to reduce the accesses of the dynamic branch predictor. Accordingly, the power consumption of the traditional dynamic branch predictor exercised every cycle can be reduced. In the proposed scheme, the branch target buffer, BTB, is modified to record the number of non-branch instructions for the corresponding entry. In the instruction fetch stage, the BTB is read out not only the target address but also the number of upcoming non-branch instructions till encountering the next branch instruction. According to those numbers, the proposed scheme can save the power consumption of the dynamic branch predictor by eliminating unnecessary lookups. Wattch and SPECcpu2000 integer and floating-point benchmarks are used to evaluate the power and the performance of the proposed scheme. SimpleScalar v3.0 is employed to simulate the proposed architecture. Simulation results show that the dynamic branch predictor power is reduced by 63.79% and 76.58% in average for SPECint2000 and SPECfp2000 respectively with negligible performance loss as compare to the based architecture.

參考文獻


[1] Seung Il Sonh, Hoon Mo Yang, Moon Key Lee,” An Implementation of Branch Target Buffer for High Performance Applications”, International Conference on Microelectronics and VLSI, Nov. 1995, pp.492 – 495.
[2] Henning, J.L., “SPEC CPU2000: measuring CPU performance in the New Millennium,” IEEE Magazines on Computer, vol. 33, no. 7, pp. 28 – 35, July 2000.
[3] Patterson, D.A., Hennessy, J.L., “Computer Architecture: A Quantitative Approach, third edition,” Morgan Kaufmann, Los Altas, 2003.
[4] Petrov, P., Orailoglu, A., “Low-power Branch Target Buffer for Application-Specific Embedded Processors,” IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 4, pp. 482 – 488, September 2003.
[5] Shuai Wang, Jie Hu, Sotirios G. Ziavras., “BTB Access Filtering: A Low Energy and High Performance Design,” In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), pp. 81-86.

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