嵌入式多核心系統之效能量測與分析

The Performance Evaluation and Analysis of Embedded Multi-core System

賴昱勳(Yu-Hsun Lai)

指導教授 ： 曾嘉影

大同大學/電機資訊學院/資訊工程學系所/碩士(2010年)

摘要

近年來由於物理因素上的限制，處理器時脈提升漸趨停滯，因此嵌入式系統為了提高效能和減低功率消耗，而開始採用多核心的技術。
目前嵌入式系統之測試程式仍然專注於單核心系統測試，並不能充分發揮和評估平行硬體架構的優勢以及性能。本論文提出了利用多核心架構的平行化程式架構和函式庫修改Integer Sort(IS)、Conjugate Gradient(CG)、Susan Smoothing(SS)、Blowfish encrypt(BF)、Fast Fourier Transform(FFT)以及Mpeg2encode六個測試程式，並且對使用現場可程式化邏輯閘陣列(Field Programmable Gate Array，FPGA)建置之NIOS II四核心系統進行效能評估與分析。測試結果顯示這六個平行測試程式運作於此平台之效能有明顯的提升，其中尤以SS之3.2倍的計算加速為最。本論文為開發嵌入式多核心平台之架構提供了一種測試方式以作為未來硬體開發之改進依據。

關鍵字

嵌入式系統 ； 多核心系統 ； 平行化程式設計 ； 效能量測

並列摘要

Recently years, as the on physical limitations, the current processor to enhance the core clock has been stuck. Therefore, multi-core technology has been introduced to embedded systems in order to improve performance and reduce power consumption.
The current benchmarks are based on single-core system, it does not fully develop and evaluate parallel hardware architecture the advantages and performance. In this thesis proposes the use of multi-core architecture of parallel programming framework and library to modify six benchmarks: Integer Sort (IS), Conjugate Gradient (CG), Susan Smoothing (SS), Blowfish encrypt (BF), Fast Fourier Transform (FFT), Mpeg2encode, and using NIOS II quad-core system of FPGA (Field Programmable Gate Array) for performance evaluation and analysis. The results showed that six of the parallel benchmarks running on this platform, the performance improved significantly, especially the SS are 3.2 times speedup. This thesis for the development of embedded multi-core platform architecture provides a test method to the future development of improved hardware basis.

並列關鍵字

Embedded System ； Multi-core System ； Parallel Programming ； Performance Evaluation

參考文獻

[8] Chunho Lee, Miodrag Potkonjak, William H. Mangion-Smith, “MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems,” Proceeding of Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture 1997, Micro-30, pages 330-335, December 1997.

[9] Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin Tseng, Yuan-Hua Chu, An-Yeu Wu, “Overview of ITRI PAC project - from VLIW DSP processor to multicore computing platform, ” Proceeding of IEEE International Symposium on VLSI Design, Automation and Test, 2008. VLSI-DAT 2008, pages 188-191, April 2008.

[10] Message Passing Interface Forum. http://www.mpi-fourm.org/.

[15] Jie Wang, Shu-Yan Zhang, Tao Liu, Zhen-Zhou Ji, Ming-Zeng Hu, “Multi-Core Embedded Processor Based on FPGA and Parallelization of SUSAN Algorithm,” Proceeding of Chinese Journal of Computers, 31(11), November 2008.

[16] Wen-Ting Zhang, Luo-Feng Geng, Duo-Li Zhang, Gao-Ming Du, Ming-Lun Gao,Wei Zhang,Ning Hou, Yi-Hua Tang, “Design of Heterogeneous MPSoC on FPGA,” Proceeding of 7th International Conference on ASIC 2007, ASICON '07, pages 102-105, October 2007.