單軌非同步電路合成之研究

Synthesis of Bundled Data Asynchronous Circuits

林柔君(Jou-Chun Lin)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2010年)

摘要

單軌(Bundled data)非同步電路具有省電、低成本以及Low EMI(電磁干擾)的優點，然而實現單軌電路卻有下列問題：其一，資料寫入時存在時序違反(Timing violations)問題，資料和Clock訊號線，須符合時序限制(Setup time及Hold time constraints)；其二，Balsa選擇Bundled data轉換的電路，在FPGA內實現，電路運作結果不正確；其三，Balsa電路模組不是參數化的設計方式，在延遲匹配(Delay matching)上需Case by Case。
因此，對於Balsa的電路元件，本論文提供參數化(Parameter)的Bundled data Library，方便容易的調整延遲，並改善原始電路的複雜性；再者，以Java語言設計合成工具，讓Balsa Breeze電路轉換成參數化的Gate-level Netlist；最後可選擇性地提供Debug訊號，根據模擬結果查看違反時序限制(Timing constraints)的訊號。
將合成轉換後的電路，配合Bundled data Library，在Alter Quartus II 9.0編譯在FPGA的實驗結果顯示，合成後的Balsa 單軌碼電路，和Balsa 雙軌碼以及Altera C2H電腦輔助設計工具的同步電路做比較，在電路成本、功率消耗以及速度上，均有相當的優勢與改善。

關鍵字

時序限制 ； 時序違反 ； Balsa設計工具 ； 單軌電路合成 ； 延遲匹配

並列摘要

Bundled data asynchronous circuits have the following advantages: low power consumption, low cost and low EMI (electromagnetic interference) compared to other types of circuits. To realize bundled data circuits, however, we must solve the following issues: first, how to add matched delays to the datapath latches or to fix timing violations (setup and hold time constraints) if edge-triggered flip flops are used. Second, how to deal with missing handshake components due to synchronous circuit optimization tool (such as Quartus). Third, how to design a parameterized handshake components to facilitate system design, debug and delay adjustment.
In this thesis, we develop a CAD tool written in Java to synthesize Balsa Breeze circuits into debugable bundled data asynchronous circuits based on a set of parameterized handshake components. The circuits are tested and verified in Altera Quartus II 9.0 and a DE2 FPGA board. The experimental results show that our bundled data asynchronous circuits outperform dual-rail asynchronous and Altera C2H synchronous circuits in terms of circuit cost, power consumption and speed.

並列關鍵字

Delay matching ； Bundled data circuit synthesis ； Timing violations ； Balsa ； Timing constraints

參考文獻

[9] Clifford E. Cummings, “New Verilog-2001 Techniques for Creating Parameterized Models”, International Hardware Description Language Conference, pp. 1–10, May. 2002.

[10] Doug Edwards, Andrew Bardsley, Lilian Janin, Luis Plana and Will Toms, “Balsa: A Tutorial Guide”, 2006.

[11] Feng Shi, Yiorgos Makris, “Testing Delay Faults in Asynchronous Handshake Circuits”, IEEE International Conference on Computer-Aided Design, pp. 193–197, Nov. 2006.

[15] Masashi Imai, Takashi Nanya, “A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations”, IEEE International Symposium on Asynchronous Circuits and Systems, pp. 68-77, Dec. 2006.

[16] Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya, “A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementation (Tool Paper)”, IEEE International Conference on Application of Concurrency to System Design, pp. 50–55, Aug. 2008.