多核心環境中減少能源消耗的快取架構

A Power Saving Cache Architecture for Multi-Core Processor

林信良(Hsin-Liang Lin)

指導教授 ： 謝忠健

大同大學/電機資訊學院/資訊工程學系所/碩士(2010年)

摘要

降低能量的消耗在現在的多核心處理器中比起效能的提升更為重要。然而在一
個處理器中快取記憶體(指令快取或是資料快取)占了將近 45%的能源消耗[1]，
所以可以降低快取記憶體的能源消耗將可以大量降低處理器的耗電量。因此提
出了一個可以適用在高效能多核心處理器的快取記憶體架構。
在這篇論文中我們提出了一個新的第 0 階層的快取，包含了一個 Filter
cache 和一個 Victim cache。犧牲快取是用來儲存當 Filter cache 的資料被取代時
就把被取代的資料放入 Victim cache 中。並且當第 0 階層接沒有所需要的資料
時才會到第一或更後面的記憶體階層來找尋資料，用此方法來減少更高階層的
快取記憶體存取次數。利用了 SimpleScalar 和 CACTI 來驗證這個架構成功減少
了指令快取和資料快取的能源消耗。如果把這架構和原本的記憶體架構做比較
可以減少將近 28%的能源消耗。並且在效能方面也比只有快取的架構有更好的
提升。

關鍵字

多核心處理器 ； 能源消耗

並列摘要

Reduce energy consumption in the current multi-core processors is more important than performance enhancement. On chip cache memory (instruction cache and data cache) accounted for nearly 45% of energy consumption [1] in a processor, reducing the energy consumption of cache memory will be able to significantly reduce processor power consumption.
In this thesis, we propose a new level-0 cache memory in the memory hierarchy. The cache contains a filter cache and a victim cache. The proposed scheme reduces the energy consumption in the instruction cache and data cache by reducing the number of accesses to the level-1 and level-2 cache.
We use a simulation infrastructure base on SimpleScalar, sim-wattch, and CACTI to evaluate our proposed scheme. Our structure saves 28% power consumption as compared to the original memory architecture without victim cache and filter cache in multi-core processor. Simulation results show that the proposed technique improve performance up to 15% compared to the conventional cache architecture.

並列關鍵字

power consumption ； filter cache ； victim cache ； multi-core

參考文獻

[1] S. Segars, “Low Power Design Techniques for Microprocessors” ISSCC, Feb 4th 2001

[2] Yen-Jen Chang, Member, IEEE “An Energy-Efficient BTB Lookup Scheme for Embedded Processors” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II:

[3] Shuai Wang, Jie Hu, and Ziavras S.G.”BTB Access Filtering: A Low Energy and High Performance Design” Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual, pp.81-86, 2008

[4] Baniasadi, A. , Moshovos, A.,”Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors” Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on, pp.458-461, 2002

[5] Rani, M., Asaduzaman, A., “Power Aware Design of Second Level Cache for Multicore Embedded Systems” IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the, pp.17-20 , 2010