全數位鎖相迴路使用高解析度數位控制振盪器

ALL DIGITAL PHASE-LOCKED LOOP WITH HIGH RESOLUTION DIGITAL CONTROLLED OSCILLATOR

徐立凡(Li-Fan Hsu)

指導教授 ： 劉皆成

大同大學/電機資訊學院/通訊工程研究所/碩士(2010年)

摘要

在這篇論文中，我們實現了一個具高解析度數位控制振盪器全數位鎖相迴路電路。當中使用時間-數位轉換器來量化相位誤差，並使用高解析度的環形控制振盪器來當作此電路的數位控制振盪器，其操作頻率範圍為212MHz~366MHz，參考訊號源為5MHz且除頻數為64時，鎖住相位的時間約為3.5 s。在本論文中使用MATLAB simulink驗證整個電路的可行性及其效能。

關鍵字

鎖相迴路 ； 全數位

並列摘要

In this thesis, we implement an all digital phase locked loop (ADPLL) with high resolution digital controlled oscillator. We use time to digital converter to quantize phase error and use a high resolution ring oscillator to be the digital controlled oscillator in the circuit. Working frequency ranges for this ADPLL is about 212~366MHz. When reference signal is 5MHz and a multiplication factor of 64, the lock-in time is about 3.5 s. The feasibility and performance of the ADPLL is verified with the MATLAB Simulink.

並列關鍵字

Phase-Locked Loop ； ADPLL

參考文獻

[1] 陳冠華, Ultra low power area efficient all digital phase-locked loop frequency synthesizer. Master Thesis, 交通大學, 2006.

[6] 王嘉斌, All Digital Frequency Synthesizers. Master Thesis, 大同大學, 2008.

[8] T. Olsson and P. Nilsson, “A Digitally Controlled PLL for SoC applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.

[2] R. E. Best, Phase-locked loops: theory, design and applications. New York McGraw-Hill, 1984.

[3] T. Olsson and P. Nilsson, “An all-Digital PLL Clock Multiplier”, ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on, 2002.