- 學位論文
使用低阻抗緩衝器之可程式低壓降線性穩壓器
PROGRAMMABLE OUTPUT LOW DROPOUT REGULATOR WITH ULTRA LOW-OUTPUT IMPEDANCE BUFFER
摘要
隨著使用電池供電的攜帶式設備迅速增加，如行動電話、筆記本電腦以及各種手持設備，提升電池的使用壽命和提供電源給晶片上的各種電路，已成為電源管理最重要的議題之一。低壓降線性穩壓器就是解決電源管理最好的應用。但是此種線性穩壓缺點之ㄧ為只有一種輸出電壓，對於不同需求的電路而言，必須再對輸出的電壓做分壓方式取得，此法對於輸入電源必定形成某重程度上的功率消耗，因此本篇論文設計一個可程式化的能隙參考電壓電路，提供給低壓降線性穩壓器作為參考電壓源，藉此達到不同電壓的輸出。參考電壓源使用PTAT（Proportional To Absolute Temperature）參考電壓電路，並結合3bit數位類比電流轉換器，達到可程式化的目的。因此輸出具有8種電壓，分別為1.8V~2.5V。採用雙並聯反饋迴路的方式使緩衝器具有低輸出阻抗，在低輸出電壓時改善頻率響應。本電路使用台積電0.35μm 2P4M CMOS製程模擬，輸入電壓3.3V下，最大輸出電流為300mA，負載電容為1μF。
並列摘要
As the use of the battery-powered portable devices such as mobile phones, laptops, and various handheld devices has been rapidly increased, power management should be one of the most important issues for maximizing the battery lifetime and providing the energy to multiple on-chip blocks. low-dropout linear regulator can be optimal power management solution for applications. But Linear regulator is only one step down and only one output voltage, the circuits for the different needs have to divide bias on output voltage. The design specifies a programmable bandgap reference voltage circuit to provide a reference voltage to low dropout linear regulator to achieve a different voltage output. Reference voltage operational amplifiers uses PTAT voltage circuit with 3bit digital to analog current converter, to achieve the purpose programmable and the output voltage with 8, respectively 1.8V ~ 2.5V. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it to improve frequency compensation for low voltage applications. The designed LDO linear regulator use TSMC 0.35μm 2P4M CMOS process technology. The input voltage 3.3V and maximum output current of 300mA while load capacitance 1μF.