全數位鎖相迴路設計

本論文所設計的全數位鎖相迴路電路實現讓相位頻率偵測器以及數位控制振盪器的時間解析度相同，並且只需經過四個參考訊號的週期時間即可產生輸出訊號。另外本論文的特色之一是採用32級的環形振盪器，而不是傳統的奇數個數振盪器，這樣可以使得相位頻率偵測器以及數位控制振盪器在解析度有共同的時間基準，藉由此特點，輸入訊號的相位偵測可以和輸出訊號的產生同步進行。在本論文的電路架構中，相位頻率偵測器以及數位控制振盪器的解析度之所以相同是因為他們共用了環形延遲迴路，而環形延遲迴路決定了時間基準，所以時間基準一樣，解析度當然也一樣，也由於這個緣故，輸出訊號的產生可以在四個參考訊號的週期時間內完成，快速達到輸出頻率的鎖定，而此頻率合成器是由硬體描述語言Verilog所寫成，並使用Modelsim軟體來做模擬及驗證此頻率合成器的設計。

關鍵字

全數位；鎖相迴路

並列摘要

In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. The generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock for a high-speed response. The frequency synthesizers are developed by Verilog, and they are simulated by Modelsim to justify the feasibility of the proposed frequency synthesizer.

並列關鍵字

all digital ； pll

參考文獻

CMOSphase-locked loop with 15 to 240 MHz locking range and 50 ps jitter,”

IEEE J. Solid-State Circuits, vol. 30, pp. 1259–1266, Nov. 1995.

[3] T. Olsson and P. Nilsson, “A digitally controlled PLL for SoC

applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp.

[5] W. Lindsey and C. Chie, “A survey of digital phase-locked loops,” Proc.

國際替代計量

全數位鎖相迴路設計

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