實體積體電路設計金屬內連線之ECO邏輯改組自動化

在布局與繞線電子設計自動化工具中，ECO繞線是後段設計至為關鍵的步驟。在功能性ECO後，晶片設計者須採用ECO繞線完成所新增及更改電路的實體連線。基於爭取上市的時間壓力，設計者往往選擇性地採用全面ECO、金屬層ECO及聚焦式離子束來完成設計之修正，並加速量產時程。現今晶片設計中，重複使用及維持現存的金屬內連線成為日趨重要的步驟，以便保持時序收斂及節省製造光罩的花費。然而市面上的後端設計工具並不完全具備如此的支援條件，尤其是無法針對光罩費用較貴的底層金屬連線進行保留及重組的工作。本研究在ECO繞線中提出freeze-layer全新解決方案，其中包含了自動偵測與改組的應用程式，以及提出繞線流程的改進，使得繞線工具進而充分利用晶片中底層的金屬連線。最後研究成果顯示出本論文題出的解決方案大為提升晶片設計的freeze-layer繞線可行性，並省下可觀的光罩開發費用。

關鍵字

ECO ；金屬層ECO ； Freeze-silicon ；繞線；預備電路元件

並列摘要

ECO routing is a key step in back-end place-and-route EDA tool. Right after functional ECO, a designer incrementally re-routes the IC design by re-connecting the new and broken nets due to ECO circuit reconstruction. Usually, due to time-to-market pressure at late design phase, Fully-ECO, Metal-Only ECO and Focused Ion Beam are selectively adopted to speed-out a chip’s production. Re-using and preserving existing routes like metal wires and vias in a design are becoming critical and important for better timing convergence and saving cost of lithography masks. However, many of current back-end tools do not fully support the feature of re-use-and-preserve existing routes, especially on lower metal layers. The cost of lithography mask synthesis on these lower layers is much higher than the others above. In this thesis, a new solution on freeze-layer ECO routing is proposed. It includes an automatic tracking and re-naming script utility and recommended routing methodology that ECO router can preserve and utilize the wire and via at lower layers. The experimental results show that the proposed ECO script utility and methodology save the manufacturing cost on lower mask layers and also optimize the design routes to achieve more possibility and layers for freeze-layer ECO routing.

並列關鍵字

Spare cell ； Route ； Freeze-Silicon ； Metal-Only ECO ； ECO ； Routing

參考文獻

[2] S.-L. Huang, C.-A. Wu, K.-F. Tang, C.-H. Hsu and C.-Y. Huang, “A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization,” in proc. Design Automation Conference, pp. 382-387, Jan. 2011.

[3] I. H.-R. Jiang and H.-Y. Chang, “Live demo: ECOS 1.0: a metal-only ECO synthesizer,” in proc. IEEE International Symposium on Circuits and Systems, pp. 2774, 2010.

[4] H.-T. Chen, C.-C. Chang and T.-T. Hwang, “New spare cell design for IR drop minimization in engineering change order,” in Proc. Design Automation Conference, pp. 402–407, July 2009.

[5] A. Jayalakshmi, “Functional ECO automation challenges and solutions,” in Proc. IEEE Asia Symposium on Quality Electronic Design, pp. 126-129, Aug. 2011

[6] S.-Y. Fang, T.-F. Chien and Y.-W. Chang, “Redundant-wires-aware ECO timing and mask cost optimization,” IEEE Transactions on Very Large Scale Integration System, pp. 381-386, Nov. 2010.

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實體積體電路設計金屬內連線之ECO邏輯改組自動化

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