Reliability Study of High Voltage Devices

Reliability Study of High Voltage Devices

何若希(Aloysius Priartanto)

指導教授 ： 許健

亞洲大學/資訊學院/資訊工程學系碩士班/碩士(2009年)

摘要

In this thesis, TCAD is used to simulate ESD and Thermal SOA
measurement. The physic models and the calibration method are discussed in order to get better accuracy on the result. GGNMOS (Grounded-Gate NMOS) as an ESD protection device for 40V BCD is used as an ESD test case. The effects of device parameter on the ESD robustness are investigated by device simulation in order to achieve the desired ESD design window. The simulated holding voltage is in agreement with BJT model that already proven has an agreement with silicon result. Finally, the proposed device has been achieved the ESD design window for 40V BCD with holding voltage above 40V and immune towards latch-up issue for 500ns TLP stress.
A novel 800V multiple RESURF LDMOS with linear p-top rings is used as
a thermal SOA test case. The effects of parameter on the thermal SOA are investigated. The thermal SOA boundary lines for different pulse time are established for this device. The simulated thermal resistance is in agreement with 3D thermal model. The Thermal SOA design tool based on Hower’s model has been re-established to justify whether the proposed layout area can fulfill the SOA
requirement or not. Finally, 2D simulation is sufficient for thermal SOA and 3D simulation for big device can be replaced by analytical solution.

關鍵字

Reliability, SOA, ESD, Thermal SOA, latch-up,TLP GGNMOS,LDMOS, BCD ； Reliability, SOA, ； Reliability, SOA,

並列摘要

In this thesis, TCAD is used to simulate ESD and Thermal SOA
measurement. The physic models and the calibration method are discussed in order to get better accuracy on the result. GGNMOS (Grounded-Gate NMOS) as an ESD protection device for 40V BCD is used as an ESD test case. The effects of device parameter on the ESD robustness are investigated by device simulation in order to achieve the desired ESD design window. The simulated holding voltage is in agreement with BJT model that already proven has an agreement with silicon result. Finally, the proposed device has been achieved the ESD design window for 40V BCD with holding voltage above 40V and immune towards latch-up issue for 500ns TLP stress.
A novel 800V multiple RESURF LDMOS with linear p-top rings is used as
a thermal SOA test case. The effects of parameter on the thermal SOA are investigated. The thermal SOA boundary lines for different pulse time are established for this device. The simulated thermal resistance is in agreement with 3D thermal model. The Thermal SOA design tool based on Hower’s model has been re-established to justify whether the proposed layout area can fulfill the SOA
requirement or not. Finally, 2D simulation is sufficient for thermal SOA and 3D simulation for big device can be replaced by analytical solution.

並列關鍵字

Reliability, SOA, ESD, Thermal SOA, latch-up,TLP GGNMOS,LDMOS, BCD ； Reliability, SOA, ； Reliability, SOA,

參考文獻

[1] P. L. Hower, “Safe operating area - a new frontier in ldmos design,” Proc.

[2] P. L. Hower, “Safe operating area considerations for analog integrated

[3] Albert Z. H. Wang, On-Chip ESD Protection for Integrated Circuits – An IC

[5] P. Hower, et al., “Avalanche-induced thermal instability in ldmos transistors,”

static and dynamic SOA (energy capability) of RESURF LDMOS devices in