A novel ESD design for 800v Ldmos with robustness

A novel ESD design for 800v Ldmos with robustness

Sarangua Enkhbaatar(Sarangua Enkhbaatar)

指導教授 ： gene sheu

亞洲大學/資訊學院/資訊工程學系碩士班/碩士(2010年)

摘要

ABSTRACT

In the power management applications, the lateral double-diffusion MOS (LDMOS) transistor with high breakdown voltage has long been integrated monolithically in IC process. These power devices are often used as the output driver, and straightly connected to the pin. Without additional Electro Static Discharge (ESD) protection devices, the power devices have to discharge the ESD stress themselves. Because of the ultra high operating voltage, the power dissipation of LDMOS under ESD stress which determined by the discharge current and the holding voltage is extremely high, thus this device is susceptible to burn out. In order to get better ESD robustness, many papers have reported an optimized structure for LDMOS: NLDMOS with an additional P+ in the drain region.
 LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor is mainly used in the Ultra high voltage application.
 The two major specifications of a LDMOS
 Low on-resistance (Ron) and high breakdown voltage.
 The major problem for LDMOS is the ESD robustness since the Ndrift is high resistive ,and the current flowline is not directly toward effective to the source contact.

關鍵字

esd ； esd ldmos ； esd ldmos

並列摘要

ABSTRACT

In the power management applications, the lateral double-diffusion MOS (LDMOS) transistor with high breakdown voltage has long been integrated monolithically in IC process. These power devices are often used as the output driver, and straightly connected to the pin. Without additional Electro Static Discharge (ESD) protection devices, the power devices have to discharge the ESD stress themselves. Because of the ultra high operating voltage, the power dissipation of LDMOS under ESD stress which determined by the discharge current and the holding voltage is extremely high, thus this device is susceptible to burn out. In order to get better ESD robustness, many papers have reported an optimized structure for LDMOS: NLDMOS with an additional P+ in the drain region.
 LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor is mainly used in the Ultra high voltage application.
 The two major specifications of a LDMOS
 Low on-resistance (Ron) and high breakdown voltage.
 The major problem for LDMOS is the ESD robustness since the Ndrift is high resistive ,and the current flowline is not directly toward effective to the source contact.

並列關鍵字

esd ldmos ； esd ldmos ； esd ldmos

參考文獻

[1] Mohammed Tanvir Quddus, Lany Tu, Takeshi Ishiguro, “Drain Voltage Dependence of On Resistance in 700V Super Junction LDMOS Transistor”, 2004 ISPSD, Page(s): 201-204

[2] Pendharkar, S, “Technology requirements for automotive electronics”, Vehicle Power and Propulsion, 2005, Page(s): 834-839

[3] Wei-Jen Chang; Ming-Dou Ker, “The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology”, Device and Materials Reliability, Vol.7 June 2007, Page(s): 324-332

[4] Naughton, John J., Tyler, Matthew, Anser, Muhammad, “Reliable High Volt Mixed Signal IC Manufacturing”, 2006. ISSM, Page(s): 407-410

[5] Vashchenko, V.A, Hopper, P.J, “A new Principle for a Self-Protecting Power Transistor Array Design”, 2007 ISPSD, Page(s): 1-4