SBATCH: An Integrated Statement-Based Parallelizing Compiler for Tightly-Coupled Heterogeneous Environments

SBATCH：一個針對緊密結合異質性計算環境所設計之整合性陳述基礎平行編譯器

朱守禮(Slo-Li Chu)

《中原學報》 32卷1期 (2004/03) Pp. 91-101

https://doi.org/10.6358/JCYU.200403.0091

摘要

智慧型記憶體是一種新的計算機結構，可以減少處理器與記憶體之間的效能差異。由於整合了不同的處理器於同一系統內，這種架構提供了一種緊密結合的異質性計算環境。為了讓應用程式能充分發揮此類架構的效能，一個有效的平行化與最佳化機制是必要的。在這份論文裡，我們以先前所發展的SAGE 系統為基礎，提出了一個整合性的架構，SBATCH，它整合了程式分割、執行時間預測，以及排程機制。我們將描述SBATCH 系統如何切割陳述以及產生執行計畫，並能充分發揮主處理器與協同處理器之效能，亦會討論其實驗結果。

關鍵字

緊密結合異質性環境 ； 陳述－基礎之分析 ； 記憶體處理器

並列摘要

Processor-in-memory is a new class of computer architecture designed for reducing the performance gap between the processor and the memory. This architecture provides a tightlycoupled heterogeneous environment by integrating different processors in a system. An efficient parallelization and optimization mechanism is necessary for this system to transform the existed applications to achieve better performance. In this paper, we propose a comprehensive framework, SBATCH, based on the statement viewpoint in our early SAGE system. It integrates program decomposition, ETC (expected time to compute) evaluation and scheduling mechanisms together. We describe how SBATCH splits statements and produces schedule to execute on the host processor and the coprocessor simultaneously. The experimental results of this approach are also discussed.

並列關鍵字

Tightly-coupled heterogeneous environment ； Statement-based analysis ； Processor-in-memory