- 期刊
算數運算處理器之快速雛型研究
A Study on Prototype of Mathematical Processor
摘要
本研究針對算數運算處理器的架構，進行快速雛型之實現與研究，將原架構為4 指令的算數運算處理器，修改少許的硬體架構，使指令增加到16個，其中包含常用的條件跳躍功能、算數與邏輯運算指令。修改後的算數運算處理器仍可實現於低閘數的FPGA/CPLD元件，且提供可執行的應用程式更具彈性，可增廣此算數運算處理器之應用範圍。另外，本研究之控制單元採用微指令方式設計，在指令修改上較具彈性，調整一些的微指令的控制步驟，並增加少許的硬體修改，可獲得多組指令的提升。實際經FPGA/CPLD元件(Lattice ispLSI1032E-70LJ84)進行雛型合成，可實現於低閘數（約6000個Gate Counts）的FPGA/CPLD之雛型建構，並通過應用程式執行之驗證。本研究對於低成本、高效能的算術運算處理器之雛型設計，可提供不錯的參考。
並列摘要
In this paper, we design the low-cost architecture circuit of mathematical processor and implement this prototype. We have modified a few architectures and controller of simple mathematical processor to increase instructions numbers from 4 to 16. Using the low-cost FPGA/CPLD device can be implemented to prototype. In addition, the controller design of architecture has used microinstruction method. It can depend on consumer demand to easy modify. We have implemented this architecture circuits of this mathematical processor chip with low-cost FPGA/CPLD device (Lattice ispLSI1032E-70LJ84), and verified this chip functions. In the experimental results of this mathematical processor chip, we have achieved goal that implement IP with low-cost FPGA/CPLD and complete this prototype.
延伸閱讀
- Huang, L. S. (2013). 快速模指數運算之研究 [doctoral dissertation, Tamkang University]. Airiti Library. https://doi.org/10.6846/TKU.2013.01286
- Lee, C. M. (2005). 進化演算法之動態分析及應用於數位濾波器之設計 [doctoral dissertation, National Central University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0031-0207200917334869
- Chen, Z. Y. (2009). 無線網路中以機器學習方法為基礎的新穎速率適應演算法 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2009.02469
- Ki, W. W. (1983). Processes in mathematics problem solving [master's thesis, The University of Hong Kong]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0029-1812201200011807
- 許建銘（2002）。The perception of more or less in solving mathematical problems。科學教育月刊，(251)，2-8。https://doi.org/10.6216/SEM.200207_(251).0001