Facility planning affects the performance of wafer fab. Better fab layout leads to shorter wafer transportation distance and lower work-in-process (WIP) level. This research applies group technology (GT) techniques to the facility planning of wafer fab. Based on the experimental design of 2^2×3×4,we build ProModel simulation models to evaluate the performance of three different fab layouts generated from different GT cell formation algorithms. The performance indices are makespan, WIP level, average cycle time, wafer transportation distance, and the average and variance of number of types of equipment in cells. Simulation results show that an algorithm proposed in this research, HNPA+, outperforms the other algorithms (such as ROCA and HNPA) in most of the perform measure.