VLSI Architecture for Serial Input Clustering Analysis

串列輸入聚類分析之VLSI架構

賴茂富(Mao-Fu Lai)

《華岡工程學報》 8期 (1995/03) Pp. 13-31

https://doi.org/10.29987/CCUHKJE.199503.0002

摘要

聚類分析在影像處理與標型辨認之應用很廣泛，最常使用之聚類分析法則爲平方誤差(Squared Error)法。由於近年來微電子之技術進步日新月異，故已發展出以VLSI實現平方誤差法，以提高聚類分析之執行速度。本文提出以收縮陣列(Systolic Array)設計聚類分析之VLSI架構，所提出之架構具有簡單、規律性、與模組化之特性，使得電路之複雜度大爲降低，同樣的架構亦可以應用在輸入資料數目改變之情況；另外因爲所提出之架構允許串列式之資料輸入，可以大量節省VLSI實現時IC之接腳數目。利用本文所提出之新架構，高速度之聚類分析可用低成本VLSI來實現。

並列摘要

Clustering analysis has numerous applications in image processing and pattern recognition. The squared error clustering algorithm is the most well-known method in clustering analysis. VLSI implementation of the squared error clustering algorithm is feasible recently due to advances in microelectronics technology. This paper presents a modular serial input VLSI architecture for the squared error clustering analysis based on systolic array. The proposed architecture features simple, regular and modular design which dramatically reduces the circuitcomplexity. Moreover, the proposed architecture can he utilized for adaptation to the change of the number of input patterns. In addition, the proposed architecture allows serial data input to save enormous pin counts, which is very attractive for VLSI implementation. Using this novel architecture, the VLSI implementation for clustering analysis can be realized cost-effectively.