最近幾年，由於人們對於無線傳輸的需求愈來愈多，使得無線網路研究領域有重大發展例如：無線區域網路、藍芽等等。再加上微型製造的技術、通訊技術及電池技術的改進，促使微小的感測器可具有感應、無線通訊及處理資訊的能力。為了節省傳輸時能量消耗，感測器的傳輸距離一般而言為數公尺至數十公尺。此類感測器多為微小及便宜的裝置，因而可大量放置於環境中形成一個感測器網路以便進行偵測任務。
IEEE 802.15.4/Zigbee 是一個適用於無線感測器網路的解決方案。它是一個針對低速無線個人網路而目標是達到低資料傳輸率、低功率以及低成本的新標準。感測器網路的設計有以下幾點是必須列為首要考量：能量消耗及生產價格。尤其是能量消耗是一個很重要的考量因素，因為在感測器網路中每個感測器的壽命可能需要維持幾個月甚至好幾年，節省功率才能使壽命增長。再加上網路中會有許多感測器，感測器的設計有可能朝向拋棄式，也就是電池沒電或是故障就直接丟棄，因此感測器成本降低才能使得整個網路的成本也降低。
在這篇論文中，我們提出Zigbee媒介存取控制層的硬體實現。這個硬體架構支援：資料傳送與接收、與網路連結或分離、載波感測多重存取碰撞避免協定。我們使用verilog設計這個硬體架構，合成依據TSMC 0.18 um 製程，最後在Xilinx FPGA發展版上做驗證。

In recent years, there are strong developments in wireless networks such as WLAN, Bluetooth, etc. IEEE 802.15.4/Zigbee is a new solution in order to be adopted in wireless sensor network. It is a new standard uniquely designed for low rate wireless personal area networks (LR-WPANs) and purposes to meet low data rate, low power consumption and low cost wireless networking.
In this thesis, we provide a hardware implementation of Zigbee Media Access Control (MAC) layer. We present a basic hardware architecture which supports data transmission and reception, association and disassociation with network and Carrier Sense Multiple Access with Collision Avoidance (CSMA-CA), etc. We use verilog to design MAC, synthesize according to TSMC 0.18um cell library and also verify by means of Xilinx FPGA

Chapter 1 Introduction 1
1.1 Motivation and objective 1
1.2 Organization of this thesis 3
Chapter 2 Background 4
2.1 MAC service specification 4
2.1.1 Data service 5
2.1.2 Management service 5
2.2 Channel access 7
2.2.1 Superframe structure 7
2.2.2 CSMA-CA Algorithm 10
2.3 Frame format 14
2.3.1 General MAC frame format 14
2.3.2 802.15.4 Individual frame type 19
Chapter 3 Design and implementation 21
3.1 Top level design 21
3.1.1 “mac_top” I/O interface 21
3.1.2 “mac_top” architecture 22
3.1.3 Design hierarchy 23
3.2 Submodules description 24
3.2.1 “parser” 25
3.2.2 “frm_gen” 26
3.2.3 “frm_tran” 27
3.2.4 “csma” 28
3.2.5 “crc” 30
3.2.6 “frm_rcv” 30
3.2.7 “frm_rtn” 32
3.2.8 “hdrfifo”, “tran_queue” and “rcv_queue” 33
3.2.9 “mac_ctrl_top” 34
Chapter 4 Experimental results 40
4.1 Design environment 40
4.2 Simulation results 41
4.2.1 Behavior simulation 41
4.2.2 FPGA verification 46
4.3 Design report 47
4.3.1 Area report 47
4.3.2 Power report 49
Chapter 5 Conclusion and future work 51
Reference 53

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