Hybrid networks, which combine the flexibility of packet-switched network and the low-latency of circuit-switched network, provide decent performance. However, existing researches require users to maintain the configuration of hybrid networks. Users need to spend a lot of time and effort on analyzing the applications at first. Then, they can know how and when to configure the hybrid network. The exhausting process motivates us to construct a hybrid network which reconfigures itself automatically. In this thesis, we propose Dynamic Bypass Circuit, a novel architecture which reconfigures the network according to the traffic trends of applications at run-time. Therefore, users need not to worry about the mapping between the applications and the network. Additionally, in order to make the trends more obvious, we modified original north-last routing algorithm into north-last-weave routing algorithm. It guides packets toward different directions according to the position of their source nodes.
The simulation results show that dynamic reconfigurable NoC which adopts Dynamic Bypass Circuit outperforms the traditional packet-switched network. The latency improvement is 18.08% under Transpose traffic and on average 10.76% under singular synthetic traffic patterns.

單晶片網路擁有優異的可擴充性及頻寬，已經逐漸地取代傳統匯流排的架構。為了追求最佳的傳輸效能，目前有許多研究是在討論混合網路的架構。混合網路結合了封包交換網路的彈性與線路交換網路的低延遲時間，它能提供優異的性能；然而，現今的研究都需要由使用者來管理混合網路的組態。使用者需要先花費大量的時間與精力來分析應用程式，然後才能知道該如何設定混合網路的組態。這種繁雜的過程給予我們靈感去建立一個能自動設定組態的混合網路。在這篇論文之中，我們分析了暫態線路交換連線對於各種封包的影響，並且提出了新穎的架構「動態旁路電路(Dynamic Bypass Circuit)」。藉由監視各個封包通過路由器的路徑，它能夠即時地偵測出應用程式的交通趨勢，並且針對這個趨勢來改變線路交換連線的組態。因此，使用者不再需要煩惱應用程式與網路的對應關係。除此之外，因為路由演算法會大幅的影響網路上的交通分佈，而這會改變動態旁路電路偵測交通的能力。為了讓交通趨勢能更顯著，我們改良原本的北向最後路由演算法(North-Last)，使之變成「編織樣式北向最後路由演算法(North-Last-Weave)」，其會參考原點的位置將封包導引到不同的方向。這個演算法能大幅提升建立暫態線路交換連線的機率。
實驗結果顯示，搭載了動態旁路電路的動態重組單晶片網路會表現的比傳統的封包交換網路要好。延遲時間的改進幅度最高為18.08%，平均改進幅度是10.76%。

Chapter 1 Introduction.................................1
1.1 The Rise of the Hybrid Networks.......................1
1.2 Motivation............................................2
1.3 Goals.................................................2
1.4 Thesis Organization...................................3
Chapter 2 Related Work.................................4
2.1 Traditional Hybrid Networks...........................4
2.2 Automatically Reconfigurable Hybrid Networks..........5
2.3 Summary...............................................6
Chapter 3 Dynamic Bypass Circuit.......................8
3.1 The Architecture of the Dynamic Reconfigurable NoC....8
3.2 Dynamic Bypass Circuit...............................10
3.3 Traffic Trend Sensing................................13
3.4 The Bypass Construction..............................19
3.5 The Bypass Destruction Process.......................23
Chapter 4 North-Last-Weave Routing Algorithm..........27
4.1 XY routing algorithm.................................27
4.2 Partially Adaptive Routing Algorithm.................29
4.3 North-Last-Weave Routing Algorithm...................31
Chapter 5 Performance Evaluation......................37
5.1 Evaluation Methodology and Platform..................37
5.2 Performance of North-Last-Weave Routing Algorithm....39
5.3 Performance of Dynamic Reconfigurable Network under Singular Synthetic Traffic Pattern.......................40
5.4 Performance of Dynamic Reconfigurable Network under Changing Traffic Pattern.................................45
Chapter 6 Conclusions and Future Work.................48
6.1 Conclusions..........................................48
6.2 Future Work..........................................49
Bibliography.............................................50

[1] W. J. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Proc. Design Automation Conference, pp. 684- 689, June 2001
[2] B. Ahmad, A. T. Erdogan and S. Khawam, "Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC," First NASA/ESA Conference on Adaptive Hardware and Systems, pp.405-411, June 2006
[3] M. Modarressi, Sarbazi-Azad H and A. Tavaakkol, "Performance and power efficient on-chip communication using adaptive virtual point-to-point connections," 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp.203-212, May 2009
[4] Shih-Hsun Hsu, Yu-Xuan Lin and Jer-Min Jou, "Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs," Solid-State Circuits Conference, pp.211-214, Nov. 2006
[5] K. Goossens, J. Dielissen and A. Radulescu, "AEthereal network on chip: concepts, architectures, and implementations," Design & Test of Computers, vol.22, no.5, pp. 414- 421, Sept.-Oct. 2005
[6] N. Enright Jerger, Li-Shiuan Peh and M. Lipasti, "Circuit-Switched Coherence," Second ACM/IEEE International Symposium on Networks-on-Chip, pp.193-202, April 2008
[7] A. Kumar, Li-Shiuan Peh, P. Kundu and N. K. Jha, "Toward Ideal On-Chip Communication Using Express Virtual Channels," Micro, IEEE , vol.28, no.1, pp.80-90, Jan.-Feb. 2008
[8] M. B. Stensgaard and J. Sparso, "ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology," Second ACM/IEEE International Symposium on Networks-on-Chip, pp.55-64, April 2008
[9] G. J. Glass and L. M. Ni, "The Turn Model for Adaptive Routing," The 19th Annual International Symposium on Computer Architecture, pp.278-287, May 1992
[10]H. G. Badr and S. Podar, "An optimal shortest-path routing policy for network computers with regular mesh-connected topologies," IEEE Transactions on Computers, vol.38, no.10, pp.1362-1371, Oct 1989
[11]W. J. Dally and H. Aoki, "Deadlock-free adaptive routing in multicomputer networks using virtual channels," IEEE Transactions on Parallel and Distributed Systems, vol.4, no.4, pp.466-475, Apr 1993
[12]Loren Schwiebert, Renelius Bell , "Performance tuning of adaptive wormhole routing through selection function choice," Journal of Parallel and Distributed Computing, v.62 n.7, p.1121-1141, July 2002
[13]G. Ascia, V. Catania, M. Palesi and D. Patti, "Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip," IEEE Transactions on Computers, vol.57, no.6, pp.809-820, June 2008
[14]"NIRGAM: A Simulator for NoC Interconnect Routing and Application Modeling," http://nirgam.ecs.soton.ac.uk/home.php, Sept 2007