鎖相迴路(PLL)是被廣泛運用在通訊系統的電路，而在現今的無線通訊系統應用中，對於相位抖動(jitter)的要求越來越來嚴格。而怎麼設計鎖相迴路在高雜訊的環境之下還能夠正常的工作，變成一個越來越重要的課題。對鎖相迴路而言，壓控振盪器(VCO)設計是一個很重要的設計考量。特別是環型壓控振盪器(ring VCO)的振盪頻率容易受到電壓源雜訊影響(supply sensitivity)，所以當電壓源有雜訊時鎖相迴路的輸出時脈訊號也會有比較大的抖動。
降低電壓源雜訊對鎖相迴路影響的方法就是減小壓控振盪器的電壓源敏感度，那解決壓控振盪器的敏感度的方法就是在壓控振盪器加入補償電路(sensitivity compensation)把敏感度補償成零。但在不同的震盪頻率下，壓控振盪器的敏感度大小和正負都是不太一樣。所以為了能夠在大操做頻率下能有較佳的效能，就必須對不同的情況做合適的補償
本研究提出具有雙向敏感度補償(bi-directional sensitivity compensation)的壓震盪器，並提出雙向自動校正(bi-directional calibration)的方法去解決壓控振盪器的正敏感(positive sensitivity)和負敏感度(negative sensitivity)的問題。除此之外，利用鎖定偵測電路自動驅動校正電路開始執行校正流程，讓鎖相迴路在額定操作頻率下都能找到一個合適的敏感度補償。
本研究的結果是模擬在TSMC 0.18um 1P6M CMOS的製程下，而電壓源的電壓是1.8V。最後藉由模擬顯示，在電壓源有頻率10MHz振幅20mV(peak-to-peak)的雜訊下，鎖相迴路操作在2.8GHz時峰對峰的抖動(peak-to-peak jitter)從25.76ps減小成13.7ps，鎖相迴路操作在1.6GHz時峰對峰的抖動從64.85ps減小成19.21ps。整體而言，藉由校正電路的功能，在操作頻率在1GHz~4GHz範圍下，壓控振盪器的敏感度能夠有效的降低，所以鎖相迴路的輸出相位抖動也都能有效降低。所提出的鎖相迴路在操作頻率為1.4GHz時消耗的功率約是16.1mW。

Phase-locked loop (PLL) is widely used in computer systems and communication systems. For a lot of applications, there often exist stringent requirement in timing jitter. Therefore, how to design a PLL which is tolerant to noise has become an important issue. In PLL, the design of voltage-controlled oscillator (VCO) is quite critical. For the wide operation frequency range applications, a ring VCO is usually employed in PLL. However, the oscillation frequency of ring VCO is sensitive to supply voltage noise. Therefore, any supply noise could degrade the jitter performance.
If the immunity against supply noise of VCO is enhanced, the output frequency will be stabilized. Therefore, a compensation circuit can be added to a VCO for reducing the supply sensitivity. Moreover, the sensitivity of VCO is varied at different operation frequencies, even may be positive or negative. As a result, adaptive sensitivity compensation is needed for robust performance over a wide operation frequency range.
We propose a bi-directional sensitivity compensation technique and a calibration technique for reducing positive and negative sensitivity of ring VCO. Besides, by using the lock detector to activate the calibration circuit automatically, an appropriate bias can be chosen to reduce the sensitivity of VCO at different operation frequencies of PLL.
The proposed design is implemented in TSMC 0.18um 1P6M CMOS technology and the supply voltage is 1.8V. With a 20mV(peak-to-peak) 10MHz sinusoidal waveform noise applied to the supply voltage, the simulated peak-to-peak jitter is improved from 25.56ps to 13.7ps at 2.8GHz operation frequency. On the other hand, the simulated peak-to-peak jitter is improved from 64.85ps to 19.21ps at 1.6GHz operation frequency. The jitter is effectively reduced over operation frequency of 1GHz to 4.0GHz. The power consumption of the proposed PLL is 16.1mW at 1.4GHz. Compared with other works, the proposed design not only provides adaptive sensitivity compensation to VCO, but also effectively reduces both positive and negative sensitivity for a wide operation frequency range.

中文摘要 i
ABSTRACT iii
List of content v
List of Figures viii
List of Tables xii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Previous techniques of supply sensitivity suppression 2
1.3 Motivation and design targets 6
1.4 Thesis organization 7
Chapter 2 Background of PLL 8
2.1 PLL structure 8
2.1.1 Phase Frequency detector (PFD) 9
2.1.2 Charge pump (CP) 13
2.1.3 Loop filter (LF) 15
2.1.4 Voltage-controlled oscillator (VCO) 17
2.1.5 Frequency divider (FD) 20
2.2 Analysis of PLL linear model 21
2.3 Supply noise analysis 30
2.4 Supply sensitivity of VCO 33
2.5 Sensitivity compensation 36
2.6 Jitter definition 38
Chapter 3 Proposed bi-directional sensitivity compensation PLL 40
3.1 Architecture of proposed PLL 40
3.2 VCO with bi-directional sensitivity compensation 41
3.3 Proposed calibration algorithm 44
3.4 Proposed calibration circuit 48
3.4.1 Supply voltage controller 53
3.4.2 Sensitivity polarity measurer (SPM) 54
3.4.3 Successive approximation register (SAR) 55
3.4.4 CLK_C generator 56
3.4.5 Lock detector 58
3.5 Multi-modulus frequency divider 61
3.6 Wide-operating range charge pump 63
3.7 PFD circuit 66
3.8 Loop filter 67
Chapter 4 Simulation result and Comparison 68
4.1 Simulation result 68
4.1.1 Behavior simulation of calibration circuit 68
4.1.2Jitter performance 72
4.1.3 Calibration transient during frequency change 76
4.2 Specification 77
4.3 Layout view 78
4.4 Comparison 79
Chapter 5 Conclusion 81
5.1 Conclusion 81
Bibliography 82

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