Abstract
Silicon (Si) has been the dominant semiconductor for electronic devices for more than four decades. However, with continued scaling of gate pitch at 0.7× per technology node, the industry has adopted strained Si and high-k dielectric technology to maintain and improve the performance of circuit during the past decade. In addtion, contact resistance and resistance-capacitance delays in the interconnect lines are also important limiting factors for device operation at the same time. Germanium (Ge) is the material with mechanical properties similar to Si. Not only Ge is infinitely soluble in Si, but also, the bulk lattice constant of Ge differs from that of Si by only 4.2%. Hence there has been more research on the use of SiGe and its potential for improving Si device performance. Furthermore, it is easier to combine with the Si-based technology today. In this work, the growth and properties of SiGe virtual substrate and Cu3Ge nanowires have been investigated.
The strain-relaxed SGOI substrate fabricated by Ge condensation is generally regarded to be an appropriate stressor for strained Si epitaxy. Investigations on the oxidation behavior and the post-annealing effect on a strained Si1-xoGexo layer (x0=0.05 and 0.10) grown on 55 nm thick SOI layer of a 8 in. SIMOX wafer were carried out. After dry thermal oxidation at 1000-1050 ℃, thin (<20 nm) SGOI layers with high Ge fraction (x>0.4) were fabricated. In addition, with two-steps oxidation treatment, it could effectively homogenize the Ge distribution in the final relaxed SiGe layer. From examinations of surface morphology of SGOI structures utilizing AFM, it was found that the HF and HCl mixed solution can etch the Ge-oxides much more effectively than only the conventional HF solution.
High-quality, thin relaxed Si0.8Ge0.2 layers grown on Si(100) by ultrahigh-vacuum chemical vapor deposition (UHVCVD) have been formed with hydrogen-implantation and subsequent thermal annealing. H+-implantation was used to introduce a layer with a high density of defects (cavities) below a 200-nm-thick strained Si0.8Ge0.2. The peak of the implanted profile was located just ~50 nm below the Si0.8Ge0.2/Si interface. The dependence of residual strain in pseudomorphic Si0.8Ge0.2 layer on the annealing temperature has been investigated. By adjusting the dose of H+-implantation and the subsequent annealing conditions, almost relaxed (~95%) Si0.8Ge0.2 layers with a smooth surface were achieved. The method provides a simple approach for the formation of thin relaxed Si0.8Ge0.2 with reduction in surface roughness for advanced complementary metal-oxide-semiconductor electronic devices.
Free-standing and single-crystal Cu3Ge nanowires were synthesized by a vapor phase deposition method in one step. The Cu3Ge nanowires are orthorhombic in structure and grown in the [010] direction. The diameters and lengths are about 20-40 nm and 4-8 □m, respectively, with aspect ratios of about 200-400. The single-crystal Cu3Ge nanowires exhibit extremely low resistivity of about 4.5-5 □□ cm, the lowest ever for a binary compound. For comparison, the resistivities of Cu3Ge thin films are in the range of 5.5-24 □□ cm. The nanowires can withstand a maximum current density of 3.2×107 A/cm2. It indicates that the Cu3Ge structure can be scaled down to ultrasmall dimensions without degradation of the electrical properties and could be a promising metal contact and interconnect candidate for the fabrication of next generation nanodevices.



摘□要
四十多年來，矽元素在電子元件中一直扮演主流半導體材料的角色。然而，隨著元件尺寸不斷縮小，業界為了維持甚至增強元件的效能，在過去十年間，已經開始採用應變矽技術以及用高介電常數/金屬閘極來取代傳統的二氧化矽/多晶矽閘極。除此之外，在金屬導線間的接觸電阻及R-C延遲效應也同時成為影響元件效能表現的重要一環。鍺元素由於與矽元素性質相近，不僅可以和矽完全互溶，而且晶格常數也僅比矽元素大4.2%，所以有越來越多的研究著重在利用矽鍺合金來增強元件的效能。在本研究中，我們將鍺元素在半導體元件上的應用為主題，探討矽鍺虛擬基材以及具有非常優異的低電阻特性的銅鍺奈米線的結構成長及性質探討。
首先，利用乾式氧化法使鍺元素濃度提升的方法，可形成應變鬆弛的絕緣層上的矽鍺層，並可被用來當作應變矽的應變源。一開始，在長有55奈米厚的矽層的SIMOX晶片上先成長具有不同鍺起始濃度的矽鍺層，本研究將探討不同的乾式氧化及後續退火條件對於應變鬆弛的絕緣層上矽鍺層的影響。在經過適當條件的氧化及退火處理後，厚度小於20奈米且具有高鍺濃度的應變鬆弛的絕緣層被成功的製備。此外，我們發現藉由兩階段退火處理，可有效的改善起始鍺濃度較高的試片在氧化後所面臨的鍺分佈不均的現象。而在利用原子力顯微鏡探討應變鬆弛的絕緣層上矽鍺層的表面平整度時，發現利用氫氟酸及鹽酸的混和液可以比傳統的單純氫氟酸更有效的去除表面的鍺氧化物的雜粒。
在第二部份研究中，利用超高真空化學氣相沉積法所成長的矽鍺層可藉由氫離子佈植法及後續的退火處理來促使應變鬆弛。在此方法中，氫離子佈植在矽鍺層與矽基材界面的下方約50奈米處。藉由改變不同的佈植濃度及不同的退火條件，將可以成功製備近乎完全應變鬆弛且具有平整界面的矽鍺層。此方法提供一個較簡易的方法來製備可以適用於先進元件的應變鬆弛矽鍺層。
在第三部份研究中，利用氣相傳輸法，獨立於試片表面且單晶結構的銅鍺奈米線第一次成功被製備。本研究所製備的銅鍺奈米線具有長方晶的單晶結構，並且沿著[010]方向成長。銅鍺奈米線的粗細範圍多介於20-40奈米且長度介於4-8微米，換算所得的長寬比則介於200-400間。特別的是，本研究所製備的銅鍺奈米線具有相當優異的低電阻性質（4.5-5 □□ cm）以及3.2×107 A/cm2的高電流密度。在現今已製備的二元化合物的奈米線中，具有最低的電阻率。除此之外，與薄膜型態的銅鍺化合物相比，銅鍺奈米線在尺寸微縮後，仍具有相當優異的電阻率，這些特性對於銅鍺奈米線在日後應用於金屬接觸及金屬間導線上具有相當大的優勢。

Contents…………………………………………………………………I
Acknowledgments……………………………………………………V
Abstract………………………………………………………………VII
List of Abbreviations and Acronyms………………………………XII
Chapter 1 SiGe Heterostructures
1.1 An Overview………………………………………………………1
1.2 Material Properties of SiGe…………………………………………4
1.2.1 Lattice Parameters and Lattice Mismatch…………………4
1.2.2 Critical Thickness of SiGe on Si……………………………7
1.3 Epitaxial Growth Techniques of SiGe………………………………9
1.3.1 Ultra-high Vacuum Chemical Vapor Deposition…………10
1.3.2 Molecular Beam Epitaxy…………………………………11
1.4 SiGe Virtual Substrates……………………………………………13
1.4.1 Introduction to SiGe Virtual Substrates…………………13
1.4.2 Mechanism of Strain Relaxation of SiGe Virtual
Substrates…………………………………………………13
1.5 Formation of Relaxed SiGe Layers………………………………16
1.5.1 Graded Buffer Technology………………………………16
1.5.2 Low Temperature Method…………………………………17
1.5.3 Chemical-mechanical Polishing (CMP) Method…………19
1.5.4 Ion Implantation Method…………………………………20
1.5.5 Ge Condensation Method…………………………………21

Chapter 2 Copper-germanide Nanostructures
2.1 An Overview of Nanotechnology…………………………………22
2.2 Applications of Metallic Nanostructures in ULSI…………………24
2.3 Material Properties of Copper Germanide…………………………26
2.3.1 Thin Film Nanostructures…………………………………26
2.3.2 Nanowire Structures………………………………………27
Chapter 3 Experimental Procedures
3.1 Ultra-high Vacuum Chemical Vapor Deposition…………………28
3.2 High Resolution XRD (HRXRD) Analysis………………………29
3.3 Transmission Electron Microscope Observation…………………30
3.4 Composition-depth Profiling Analysis by Auger Electron Spectroscope………………………………………………………31
3.5 Energy Dispersion Spectrometer (EDS) Analysis…………………31
3.6 Atomic Force Microscope (AFM) Observation……………………32
3.7 Initial Cu Substrates Cleaning……………………………………32
3.8 Thermal Vapor Deposition System………………………………32
3.9 Sample Preparations for Transmission Electron Microscope (TEM) Observation………………………………………………………33
3.9.1 Planview Specimen Preparation…………………………33
3.9.2 Cross-sectional Specimen Preparation……………………34
3.10 Scanning Electron Microscope (SEM) Observation………………35
3.11 Current-voltage (I-V) Measurements……………………………35
3.12 Focused Ion Beam (FIB) System…………………………………36



Chapter 4 Effects of Post-annealing on the Oxidation Behavior in the Formation of SiGe-on-insulator (SGOI)
4.1 Motivation…………………………………………………………37
4.2 Experimental Procedures…………………………………………40
4.3 Results and Discussion……………………………………………40
4.3.1 Microstructures and Thickness……………………………40
4.3.2 Surface Morphology………………………………………43
4.3.3 Concentration Profile of Ge………………………………44
4.4 Summary and Conclusions………………………………………46
Chapter 5 Formation of High-quality and Relaxed SiGe Buffer Layer with H+-implantation and Subsequent Thermal Annealing
5.1 Motivation…………………………………………………………47
5.2 Experimental Procedures…………………………………………49
5.3 Results and Discussion……………………………………………50
5.4 Summary and Conclusions………………………………………59
Chapter 6 Free-standing and Single-crystal Cu3Ge Nanowires with the Lowest Resistivity for Binary Compounds
6.1 Motivation…………………………………………………………60
6.2 Experimental Procedures…………………………………………62
6.3 Results and Discussion……………………………………………64
6.4 Summary and Conclusions………………………………………70


Chapter 7 Summary and Conclusions
7.1 Effects of Post-annealing on the Oxidation Behavior in the Formation of SiGe-on-insulator (SGOI).….….….….….….….….72
7.2 Formation of High-quality and Relaxed SiGe Buffer Layer with H+-implantation and Subsequent Thermal Annealing……………73
7.3 Free-standing and Single-crystal Cu3Ge Nanowires with the Lowest Resistivity for Binary Compounds…………………………………74
Chapter 8 Future Prospects
8.1 High-k/GOI MOSFETs for Future Generation Devices…………75
8.2 In Situ Transmission Electron Microscope Investigation on the Formation of the Copper Germanide Nanowires…………………76
References………………………………………………………………77

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2.29. L. Krusinelbaum and M. O. Aboelfotoh, “Unusually Low Resistivity of Copper Germanide Thin Films Formed at Low Temperatures,” Appl. Phys. Lett. 58, 1341-1343 (1991).
2.30. C. M. Chang, Y. C. Chang, Y. A. Chung, C. Y. Lee and L. J. Chen, “Synthesis and Properties of the Low Resistivity TiSi2 Nanowires Grown with TiF4 Precursor,” J. Phys. Chem. C 113, 17720-17723 (2009).
2.31. C. I. Tsai, P. H. Yeh, C. Y. Wang, H. W. Wu, U. S. Chen, M. Y. Lu, W. W. Wu, L. J. Chen and Z. L. Wang, “Cobalt Silicide Nanostructures: Synthesis, Electron Transport, and Field Emission Properties,” Cryst. Growth Des. 9, 4514-4518 (2009).
2.32. C. J. Kim, K. Kang, Y. S. Woo, K. G. Ryu, H. Moon, J. M. Kim, D. S. Zang and M. H. Jo, “Spontaneous Chemical Vapor Growth of NiSi Nanowires and Their Metallic Properties,” Adv. Mater. 19, 3637-3642 (2007).
2.33. C. Y. Lee, M. P. Lu, K. F. Liao, W. W. Wu and L. J. Chen, “Vertically Well-aligned Epitaxial Ni31Si12 Nanowire Arrays with Excellent Field Emission Properties,” Appl. Phys. Lett. 93, 113109 (2008).
2.34. C. Y. Lee, M. P. Lu, K. F. Liao, W. F. Lee, C. T. Huang, S. Y. Chen and L. J. Chen, “Free-standing Single-crystal NiSi Nanowires with Excellent Electrical Transport and Field Emission Properties,” J. Phys. Chem. C 113, 2286-2289 (2009).
2.35. Y. Wu, J. Xiang, C. Yang, W. Lu and C. M. Lieber, “Single-crystal Metallic Nanowires and Metal/Semiconductor Nanowire Heterostructures,” Nature 430, 61-66 (2004).
2.36. Y. P. Song, A. L. Schmitt and S. Jin, “Ultralong Single-crystal Metallic Ni2Si Nanowires with Low Resistivity,” Nano Lett. 7, 965-969 (2007).
2.37. M. O. Aboelfotoh, C. L. Lin and J. M. Woodall, “Novel Low-resistance Ohmic Contact to N-type GaAs Using Cu3Ge,” Appl. Phys. Lett. 65, 3245-3247 (1994).
2.38. M. O. Aboelfotoh, M. A. Borek and J. Narayan, “Ohmic Contact to P-type GaAs Using Cu3Ge,” Appl. Phys. Lett. 75, 3953-3955 (1999).
2.39. M. O. Aboelfotoh and H. M. Tawancy, “Effect of Crystal Structure on the Electrical Resistivity of Copper-germanium Thin-film Alloys,” J. Appl. Phys. 75, 2441-2446 (1994).
2.40. H. K. Liou, J. S. Huang and K. N. Tu, “Oxidation of Cu and Cu3Ge Thin Films,” J. Appl. Phys. 77, 5443-5445 (1995).
2.41. M. A. Borek, S. Oktyabrsky, M. O. Aboelfotoh and J. Narayan, “Low Resistivity Copper Germanide on (100) Si for Contacts and Interconnections,” Appl. Phys. Lett. 69, 3560-3562 (1996).
2.42. Y. L. Chao, Y. Xu, R. Scholz and J. C. S. Woo, “Characterization of Copper Germainde as Contact Metal for Advanced MOSFETs,” IEEE Electron Device Lett. 27, 549-551 (2006).
2.43. Y. L. Chao and J. C. S. Woo, “Source/Drain Engineering for Parasitic Resistance Reduction for Germanium p-MOSFETs,” IEEE Trans. Electron Devices 54, 2750-2755 (2007).
2.44. T. Burchhart, A. Lugstein, Y. J. Hyun, G. Hochleitner and E. Bertagnolli, “Atomic Scale Alignment of Copper-germanide Contacts for Ge Nanowires Metal Oxide Field Effect Transistors,” Nano Lett. 9, 3739-3742 (2009).

Chapter 3
3.1. B. S. Meyerson, “UHV/CVD Growth of Si and Si:Ge Alloys: Chemicstry, Physics, and Device Applications,” Proc. IEEE 80, 1592-1608 (1992).
3.2. A. Ishizaka and Y. Shiraki, “Low Temperature Surface Cleaning of Silicon and its Application to Silicon MBE,” J. Electrochem. Soc. 133, 666-671 (1976).
3.3. S. K. Lee, Y. H. Ku and D. L. Kwong, “Silicon Epitaxial Growth by Rapid Thermal Processing Chemical Vapor Deposition,” Appl. Phys. Lett. 54, 1775-1777 (1989).
3.4. A. D. Lambert, B. M. McGregor, R. J. H. Morris, C. P. Parry, D. P. Chu, G. A. Cooke, P. J. Phillips, T. E. Whall and E. H. C. Parker, “Contamination Issues During Atomic Hydrogen Surfactant Mediated Si MBE,” Semicond. Sci. Technol. 14, L1-L4 (1999).
3.5. T. T. Sheng and C. C. Chang, “Transmission Electron Microscope of Cross Section of Large Scale Integrated Circuits,” IEEE Trans. Electron Devices 23, 531-553 (1976).
3.6. R. H. Fowler and L. W. Nordheim, “Electron Emission in Intense Electric Fields,” Proc. R. Soc. London, Ser. A 119, 173 (1928).
3.7. C. Y. Lee, T. Y. Tseng, S. Y. Li and P. Lin, “Single-crystalline MgxZn1-xO (0≦x≦0.25) Nanowires on Glass Substrates Obtained by a Hydrothermal Method: Growth, Structure and Electrical Characteristics,” Nanotechnol. 16, 1105-1111 (2005).

Chapter 4
4.1. T. Mizuno, N. Sugiyama, T. Tezuka and S. Takagi, “Novel SOI p-channel MOSFETs with Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Trans. Electron Devices 49, 7-14 (2002).
4.2. T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata and S. Takagi, “High-performance Strained-SOI CMOS Devices Using Thin Film SiGe-on-insulator Technology,” IEEE Trans. Electron Devices 50, 988-994 (2003).
4.3. S. F. Nelson, K. Ismail, J. O. Chou and B. S. Meyerson, “Room-temperature Electron-mobility in Strained Si/SiGe Heterostructures.” Appl. Phys. Lett. 63, 367-369 (1993).
4.4. J. B. Roldan, F. Gamiz, J. A. LopezVillanueva and J. E. Carceller, “A Monte Carlo Study on the Electron-transport Properties of High-performance Strained-Si on Relaxed Si1-xGex Channel MOSFETs,” J. Appl. Phys. 80, 5121-5128 (1996).
4.5. A. R. Powell, S. S. Iyer and F. K. LeGoues, “New Approach to the Growth of Low Dislocation Relaxed SiGe Material,” Appl. Phys. Lett. 64, 1856-1858 (1994).
4.6. K. Brunner, H. Dobler, G. Abstreiter, H. Scha¨fer and B. Lustig, “Molecular Beam Epitaxy Growth and Thermal Stability of Si1-xGex Layers on Extremely Thin Silicon-on-insulator Substrates,” Thin Solid Films 321, 245-250 (1998).
4.7. F. Y. Huang, M. A. Chu, M. O. Tanner, K. L. Wang, G. D. U’Ren and M. S. Goorsky, “High-quality Strain-relaxed SiGe Alloy Grown on Implanted Silicon-on-insulator Substrate,” Appl. Phys. Lett. 76, 2680-2682 (2000).
4.8. L.-J. Huang, J. O. Chu, S. A. Goma, C. P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes, J. L. Speidell, R. M. Anderson and H.-S. P. Wong, Proceedings of the 2001 Symposium on VLSI Technology, Kyoto, Japan Society of Applied Physics, Tokyo, p. 57 (2001).
4.9. T. Tezuka, N. Sugiyama and S. Takagi, “Fabrication of Strained Si on an Ultrathin SiGe-on-insulator Virtual Substrate with a High-Ge Fraction,” Appl. Phys. Lett. 79, 1798-1800 (2001).
4.10. F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel and B. S. Meyerson, “Oxidation Studies of SiGe,” J. Appl. Phys. 65, 1724-1728 (1989).
4.11. T. Tezuka, N. Sugiyama, T. Mizuno, M. Suzuki and S. Takagi, “A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 run Strained Silicon-on-insulator MOSFETs,” Jpn. J. Appl. Phys. Part 1 - Regul. Pap. Short Notes Rev. Pap. 40, 2866-2874 (2001).
4.12. L. T. Su, J. B. Jacobs, J. E. Chung and D. A. Antoniadis, “Deep-submicrometer Channel Design in Silicon-on-insulator (SOI) MOSFET,” IEEE Electron Device Lett. 15, 366-369 (1994).
4.13. D. Fathy, O. W. Holland and C. W. White, “Formation of Epitaxy Layers of Ge on Si Substrates by Ge Implantation and Oxidation,” Appl. Phys. Lett. 51, 1337-1339 (1987).
4.14. B. Onsia, et al., “Ultra Clean Processing of Silicon Surfaces Vii”, edited by P. Mertens, M. Meuris and M. Heyns (Trans Tech Publications Ltd, Zurich-Uetikon), 103-104, 19-22 (2005).
4.15. D. Bodlaki, H. Yamamoto, D. H. Waldeck and E. Borguet, “Ambient Stability of Chemically Passivated Germanium Interfaces,” Surf. Sci. 543, 63-74 (2003).
Chapter 5
5.1. S. S. Iyer, G. L. Patton, J. M. C. Stock, B. S. Meyerson and D. L. Harame, “Heterojunction Bipolar-transistors Using Si-Ge Alloys,” IEEE Trans. Electron Devices 36, 2043-2064 (1989).
5.2. G. L. Patton, J. H. Comfort, B. S. Meyerson, E. F. Crabbe, G. J. Scilla, E. Defresart, J. M. C. Stork, J. Y. C. Sun, D. L. Harame and J. N. Burghartz, “75-GHz Ft SiGe-base Heterojunction Bipolar-transistors,” IEEE Electron Device Lett. 11, 171-173 (1990).
5.3. P. M. Mooney, “The Strain Relaxation and Dislocations in SiGe/Si Structures,” Mater. Sci. Eng. 17, 105-146 (1996).
5.4. F. K. LeGoues, B. S. Meyerson, J. F. Morar and P. D. Kirchner, “Mechanism and Conditions for Anomalous Strain Relaxation in Graded Thin-films and Superlattices,” J. Appl. Phys. 71, 4230-4243 (1992).
5.5. F. K. LeGoues, “The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface,” MRS Bull. 21, 38-44 (1996).
5.6. E. A. Fitzgerald, Y. H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Michel, Y. J. Mii and B. E. Weir, “Totally Relaxed GexSi1-x Layers with Low Threading Dislocation Densities Grown on Si Substrates,” Appl. Phys. Lett. 59, 811-813 (1991).
5.7. T. Hackbarth, H. J. Herzog, K. H. Hieber, U. Konig, M. Bollani, D. Chrastina and H. von Kanel, “Reduced Self-heating in Si/SiGe Field-effect Transistors on Thin Virtual Substrates Prepared by Low-energy Plasma-enhanced Chemical Vapor Deposition,” Appl. Phys. Lett. 83, 5464-5466 (2003).
5.8. K. K. Linder, F. C. Zhang, J. S. Rieh, P. Bhattacharya and D. Houghton, “Reduction of Dislocation Density in Mismatched SiGe/Si Using a Low-temperature Si Buffer Layer,” Appl. Phys. Lett. 70, 3224-3226 (1997).
5.9. H. Chen, L. W. Guo, Q. Cui, Q. Hu, Q. Huang and J. M. Zhou, “Low-temperature Buffer Layer for Growth of a Low-dislocation-density SiGe Layer on Si by Molecular-beam Epitaxy,” J. Appl. Phys. 79, 1167-1169 (1996).
5.10. J. H. Li, C. S. Peng, Y. Wu, D. Y. Dai, J. M. Zhou and Z. H. Mai, “Relaxed Si0.7Ge0.3 Layers Grown on Low-temperatures Si Buffers with Low Threading Dislocation Density,” Appl. Phys. Lett. 71, 3132-3134 (1997).
5.11. B. Hollander, S. Mantl, R. Liedtke, S. Mesters, H. J. Herzog, H. Kibbel and T. Hackbarth, “Enhanced Strain Relaxation of Epitaxial SiGe Layers on Si(100) after H+ Ion Implantation,” Nuclear Instrum. and Methods in Phys. Res. B, 148, 200-210 (1999).
5.12. S. Mantl, B. Hollander, R. Liedtke, S. Mesters, H. J. Herzog, H. Kibbel and T. Hackbarth, “Strain Relaxation of Epitaxial SiGe Layers on Si(100) Improved by Hydrogen Implantation,” Nuclear Instrum. and Methods in Phys. Res. B, 147, 29-34 (1999).
5.13. E. Kasper, K. Lyutovich, M. Bauer and M. Oehme, “New Virtual Substrate Concept for Vertical MOS Transistors,” Thin Solid Films, 336, 319-322 (1998).
5.14. G. F. Ceroeolini and G. Ottaviani, “Hydrogen in Silicon-state, Reactivity and Evolution after Ion-implantation,” Mat. Sci. Eng. 4, 19-24 (1989).
5.15. F. K. LeGoues, A. Powell, S. S. Iyer, “Relaxation of SiGe Thin-films Grown on Si/SiO2 Substrates,” J. Appl. Phys. 75, 7240-7246 (1994).
5.16. S. Christiansen, M. Albrecht, J. Michler and H. P. Strunk, “Elastic and Plastic Relaxation in Slightly Undulated Misfitting Epitaxial Layers - A Quantitative Approach by Three-dimensional Finite Element Calculations,” Phys. Stat. Sol. A 156,129-150 (1996).
5.17. C. S. Ozkan, W. D. Nix and H. Gao, “Strain Relaxation and Defect Formation in Heteroepitaxial Films via Surface Roughening Induced by Controlled Annealing Experiments,” Appl. Phys. Lett. 70, 2247-2249 (1997).

Chapter 6
6.1. K. A. Dean and B. R. Chalamala, “The Environmental Stability of Field Emission from Single-walled Carbon Nanotubes,” Appl. Phys. Lett. 75, 3017-3019 (1999).
6.2. X. F. Duan, Y. Huang, Y. Cui, J. F. Wang and C. M. Lieber, “Indium Phosphide Nanowires as Building Blocks for Nanoscale Electronic and Optoelectronic Devices,” Nature 409, 66-69 (2001).
6.3. L. J. Chen, “Metal Silicides: An Integral Part of Microelectronics,” JOM 57(9), 24-30 (2005).
6.4. K. C. Chen, W. W. Wu, C. N. Liao, L. J. Chen and K. N. Tu, “Observation of Atomic Diffusion at Twin-modified Grain Boundaries in Copper,” Science 321, 1066-1069 (2008).
6.5. Y. C. Lin, K. C. Lu, W. W. Wu, J. W. Bai, L. J. Chen, K. N. Tu and Y. Huang, “Single Crystalline PtSi Nanowires, PtSi/Si/PtSi Nanowire Heterostructures, and Nanodevices,” Nano Lett. 8, 913-918 (2008).
6.6. Y. C. Chou, W. W. Wu, L. J. Chen and K. N. Tu, “Homogeneous Nucleation of Epitaxial CoSi2 and NiSi in Si Nanowires,” Nano Lett. 9, 2337-2342 (2009).
6.7. Y. Kamata, “High-k/Ge MOSFETs for Future Nanoelectronics,” Mater. Today 11, 30-38 (2008).
6.8. J. A. Kittl, K. Opsomer, C. Torregiani, C. Demeurisse, S. Mertens, D. P. Brunco, M. J. H. Van Dal and A. Lauwers, “Silicides and Germanides for Nano-CMOS Applications,” Mater. Sci. Eng. B-Solid State Mater. Adv. Technol. 154-155, 144-154 (2008).
6.9. E. Simoen, K. Opsomer, C. Claeys, K. Maex, C. Detavernier, R. L. Van Meirhaeghe and P. Clauws, “Study of Metal-related Deep-level Defects in Germanide Schottky Barriers on N-type Germanium,” J. Appl. Phys. 104, 023705 (2008).
6.10. S. L. Zhang and M. Ostling, “Metal Silicides in CMOS Technology: Past, Present, and Future Trends,” Crit. Rev. Solid State Mat. Sci. 28, 1-129 (2003).
6.11. L. Krusinelbaum and M. O. Aboelfotoh, “Unusually Low Resistivity of Copper Germanide Thin Films Formed at Low Temperatures,” Appl. Phys. Lett. 58, 1341-1343 (1991).
6.12. C. M. Chang, Y. C. Chang, Y. A. Chung, C. Y. Lee and L. J. Chen, “Synthesis and Properties of the Low Resistivity TiSi2 Nanowires Grown with TiF4 Precursor,” J. Phys. Chem. C 113, 17720-17723 (2009).
6.13. C. I. Tsai, P. H. Yeh, C. Y. Wang, H. W. Wu, U. S. Chen, M. Y. Lu, W. W. Wu, L. J. Chen and Z. L. Wang, “Cobalt Silicide Nanostructures: Synthesis, Electron Transport, and Field Emission Properties,” Cryst. Growth Des. 9, 4514-4518 (2009).
6.14. C. J. Kim, K. Kang, Y. S. Woo, K. G. Ryu, H. Moon, J. M. Kim, D. S. Zang and M. H. Jo, “Spontaneous Chemical Vapor Growth of NiSi Nanowires and their Metallic Properties,” Adv. Mater. 19, 3637-3642 (2007).
6.15. C. Y. Lee, M. P. Lu, K. F. Liao, W. W. Wu and L. J. Chen, “Vertically Well-aligned Epitaxial Ni31Si12 Nanowire Arrays with Excellent Field Emission Properties,” Appl. Phys. Lett. 93, 113109 (2008).
6.16. C. Y. Lee, M. P. Lu, K. F. Liao, W. F. Lee, C. T. Huang, S. Y. Chen and L. J. Chen, “Free-standing Single-crystal NiSi Nanowires with Excellent Electrical Transport and Field Emission Properties,” J. Phys. Chem. C 113, 2286-2289 (2009).
6.17. Y. Wu, J. Xiang, C. Yang, W. Lu and C. M. Lieber, “Single-crystal Metallic Nanowires and Metal/Semiconductor Nanowire Heterostructures,” Nature 430, 61-66 (2004).
6.18. Y. P. Song, A. L. Schmitt and S. Jin, “Ultralong Single-crystal Metallic Ni2Si Nanowires with Low Resistivity,” Nano Lett. 7, 965-969 (2007).
6.19. S. L. Cheng, “The Study of Formation and Thermal Stability of Titanium Silicide Thin Films in Deep Submicron Devices,” Ph. D Thesis, National Tsing-Hwa University, Hsinchu, Taiwan, ROC (1999).
6.20. J. B. Lai, “Interfacial Reactions of Titanium and Copper Thin Films on Si-Ge Alloys on Silicon and Germanium,” Ph. D Thesis, National Tsing-Hwa University, Hsinchu, Taiwan, ROC (1999).
6.21. R. Li, S. J. Lee, H. B. Yao, D. Z. Chi, M. B. Yu and D.-L. Kwong, “Pt-germanide Schottky Source/Drain Germanium p-MOSFETs with HfO2 Gate Dielectric and TaN Gate Electrode,” IEEE Electron Device Lett. 27, 476–478, (2006).
6.22. J. Y. Spann, R. A. Anderson, T. J. Thornton, G. Harris, S. G. Thomas and C. Tracy, “Characterization of Nickel Germanide Thin Films for Use as Contacts to p-channel Germanium MOSFETs,” IEEE Electron Device Lett. 26, 151-153 (2005).
6.23. S. Y. Zhu and A. Nakajima, “Annealing Temperature Dependence on Nickel-germanium Solid-state Reaction” Jpn. J. Appl. Phys. 44, 753-755 (2005).
6.24. S. P. Ashburn, M. C. Ozturk, G. Harris and D. M. Maher, “Phase-transitions During Solid-state Formation of Cobalt Germanide by Rapid Thermal Annealing,” J. Appl. Phys. 74, 4455-4460 (1993).
6.25. N. Lundberg, M. Ostling and F. M. Dheurle, “Chromium Germanides - Formation, Structure and Properties,” Appl. Surf. Sci. 53, 126-131 (1991).
6.26. M. Setton and J. Vanderspiegel, “Structural and Electrical Properties of ZrSi2 and Zr2CuSi4 Formed by Rapid Thermal Processing,” J. Appl. Phys. 70, 193-197 (1991).
6.27. M. O. Aboelfotoh, C. L. Lin and J. M. Woodall, “Novel Low-resistance Ohmic Contact to N-type GaAs Using Cu3Ge,” Appl. Phys. Lett. 65, 3245-3247 (1994).
6.28. M. O. Aboelfotoh, M. A. Borek and J. Narayan, “Ohmic Contact to P-type GaAs Using Cu3Ge,” Appl. Phys. Lett. 75, 3953-3955 (1999).
6.29. M. O. Aboelfotoh and H. M. Tawancy, “Effect of Crystal Structure on the Electrical Resistivity of Copper-germanium Thin-film Alloys,” J. Appl. Phys. 75, 2441-2446 (1994).
6.30. H. K. Liou, J. S. Huang and K. N. Tu, “Oxidation of Cu and Cu3Ge Thin Films,” J. Appl. Phys. 77, 5443-5445 (1995).
6.31. M. A. Borek, S. Oktyabrsky, M. O. Aboelfotoh and J. Narayan, “Low Resistivity Copper Germanide on (100) Si for Contacts and Interconnections,” Appl. Phys. Lett. 69, 3560-3562 (1996).
6.32. Y. L. Chao, Y. Xu, R. Scholz and J. C. S. Woo, “Characterization of Copper Germainde as Contact Metal for Advanced MOSFETs,” IEEE Electron Device Lett. 27, 549-551 (2006).
6.33. Y. L. Chao and J. C. S. Woo, “Source/Drain Engineering for Parasitic Resistance Reduction for Germanium p-MOSFETs,” IEEE Trans. Electron Devices 54, 2750-2755 (2007).
6.34. M. O. Aboelfotoh, K. N. Tu, F. Nava and M. Michelini, “Electrical Transport Properties of Cu3Ge Thin Films,” J. Appl. Phys. 75, 1616-1619 (2004).
6.35. S. Dhar, T. Som, Y. N. Mohapatra and V. N. Kulkarni, “Room-temperature Synthesis of Copper Germanide Phase by Ion Beam Mixing,” Appl. Phys. Lett. 67, 1700-1702 (1995).
6.36. J. S. Huang, S. S. Huang, K. N. Tu, F. Deng, S. S. Lau, S. L. Cheng and L. J. Chen, “Kinetics of Cu3Ge formation and Reaction with Al,” J. Appl. Phys. 82, 644-649 (1997).
6.37. J. B. Lai and L. J. Chen, “Phase Formation and Electrical Resistivity of Ultrahigh Vacuum Deposited Cu Thin Films on Epitaxial Si-Ge Layers on Si and Ge,” J. Appl. Phys. 87, 2237-2244 (2000).
6.38. L. J. Chen, C. S. Liu and J. B. Lai, “Interfacial reactions of Ultrahigh-vacuum-deposited Cu Thin Films on Si, Ge and on Epitaxial Si-Ge Layers on Si and Ge,” Mater. Sci. Semicond. Process. 7, 143-156 (2004).
6.39. T. Burchhart, A. Lugstein, Y. J. Hyun, G. Hochleitner and E. Bertagnolli, “Atomic Scale Alignment of Copper-germanide Contacts for Ge Nanowires Metal Oxide Field Effect Transistors,” Nano Lett. 9, 3739-3742 (2009).
6.40. S. Q. Hong, C. M. Comrie, S. W. Russell and J. W. Mayer, “Phase Formation in Cu-Si and Cu-Ge,” J. Appl. Phys. 70, 3655-3660 (1991).
6.41. C. L. Hsin, J. H. He, C. Y. Lee, W. W. Wu, P. H. Yeh, L. J. Chen and Z. L. Wang, “Lateral Self-aligned P-type In2O3 Nanowire Arrays Epitaxially Grown on Si Substrates,” Nano Lett. 7, 1799-1803 (2007).
6.42. S. M. Rossnagel and T. S. Kuan, “Alteration of Cu Conductivity in the Size Effect Regime,” J. Vac. Sci. Technol. B 22, 240-245 (2004).
6.43. W. Wu, S. H. Brongersma, M. Van Hove and K. Maex, “Influence of Surface and Grain-boundary Scattering on the Resistivity of Copper in Reduced Dimensions,” Appl. Phys. Lett. 84, 2838-2840 (2004).
6.44. H. Marom, J. Mullin and M. Eizenberg, “Size-dependent Resistivity of Nanometric Copper Wires,” Physical Review B 74, 045411 (2006).

Chapter 8
8.1. S. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, Anand Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B Tufts, S. Tyagi, M Bohr and Y. Mansy, “A 90-nm Logic Technology Featuring Strained-silicon,” IEEE Trans. Electron Devices 51, 1790-1797 (2004).
8.2. P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang and M. Bohr, “A 65 nm Logic Technoloty Featuring 35 nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 □m2 SRAM Cell,” Inter. Elec. Dev. Meet. 657-660 (2004).
8.3. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstorm, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seipe, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troegerm P. Vandervoorn, S. Williams and K. Zawadzki, “A 45 nm Logic Technology with High-k/Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging,” Inter. Elec. Dev. Meet. 247-250 (2007).
8.4. Q. X. Xu, X. F. Duan, H. H. Liu, Z. S. Han and T. C. Ye, “Low-cost and Highly Manufacturable Strained-Si Channel Technology for Strong Hole Mobility Enhancement on 35-nm Gate Length p-MOSFETs,” IEEE Trans. Electron Devices 54, 1394-1401 (2007).
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